Uceda, A.
2014  Ergebnisse:
Personensuche X
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2

How to model a DC microgrid: Towards an automated solution:

, In: 2017 IEEE Second International Conference on DC Microgrids (ICDCM),
Frances, A. ; Asensi, R. ; Garcia, O... - p. 609-616 , 2017
 
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3

Uropatía obstructiva litiásica con rotura de fórnix calicia..:

Alandete, S. ; Uceda, D. ; Monedero, M.D.
Revista Argentina de Radiología.  80 (2016)  4 - p. 295-297 , 2016
 
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4

Muscle impairment in Whipple's disease. A case report:

Maeztu, M.C. ; Moreno, J. ; Uceda, A...
Neurophysiologie Clinique/Clinical Neurophysiology.  43 (2013)  5-6 - p. 321 , 2013
 
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5

IMS: A new technology to develop a telemedicine system:

, In: 2008 30th Annual International Conference of the IEEE Engineering in Medicine and Biology Society,
Uceda, J.D. ; Elena, M. ; Blasco, S... - p. None , 2008
 
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6

Design of a Remote Monitoring Platform for Telemedicine Sys..:

, In: 2008 International Conference on Complex, Intelligent and Software Intensive Systems,
Blasco, S. ; Uceda, J.D. ; Elena, M.. - p. None , 2008
 
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7

Designing inductors at device and converter level:

, In: Industrial Electronics, 2002. ISIE 2002. Proceedings of the 2002 IEEE International Symposium on,
Prieto, R. ; Garcia, O. ; Cobos, J.A.. - p. None , 2002
 
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8

High efficiency PFC converter to meet EN61000-3-2 and A14:

, In: Industrial Electronics, 2002. ISIE 2002. Proceedings of the 2002 IEEE International Symposium on,
Garcia, O. ; Cobos, J.A. ; Uceda, J. - p. None , 2002
 
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9

Nonintrusive debugging using the JTAG interface of FPGA-bas..:

, In: Industrial Electronics, 2002. ISIE 2002. Proceedings of the 2002 IEEE International Symposium on,
de la Torre, E. ; Garcia, M. ; Riesgo, T... - p. None , 2002
 
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10

A system-on-chip for smart sensors:

, In: Industrial Electronics, 2002. ISIE 2002. Proceedings of the 2002 IEEE International Symposium on,
de Castro, A. ; Chaquet, J.M. ; Morejon, E... - p. None , 2002
 
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12

Quality estimation of test vectors and functional validatio..:

, In: Proceedings of the conference on Design, automation and test in Europe,
Riesgo, T. ; Torroja, Y. ; de la Torre, E.. - p. 955-956 , 1998
 
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13

A fault model for VHDL descriptions at the register transfe..:

, In: Proceedings of the conference on European design automation,
Riesgo, T. ; Uceda, J. - p. 462-467 , 1996
 
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14

Model generation of test logic for macrocell based designs:

, In: Proceedings of the conference on European design automation,
de la Torre, E. ; Calvo, J. ; Uceda, J. - p. 456-461 , 1996
 
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15

Timing optimization by an improved redundancy addition and ..:

, In: Proceedings of the conference on European design automation,
Entrena, L. ; Olías, E. ; Uceda, J.. - p. 342-347 , 1996
 
1-15
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