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VALLERO, ALESSANDRO
52  Ergebnisse:
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1

Performance Monitor Counters: Interplay Between Safety and ..:

Carelli, Alberto ; Vallero, Alessandro ; Di Carlo, Stefano
IEEE Transactions on Device and Materials Reliability.  19 (2019)  1 - p. 73-83 , 2019
Link: https://doi.org/10.1109/..
 
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2

Combining Cluster Sampling and ACE analysis to improve faul..:

, In: 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT),
Vallero, Alessandro ; di Carlo, Stefano - p. 8138-8143 , 2019
Link: https://doi.org/10.1109/..
 
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3

ReDO: Cross-Layer Multi-Objective Design-Exploration Framew..:

Savino, Alessandro ; Vallero, Alessandro ; Di Carlo, Stefano
IEEE Transactions on Computers.  67 (2018)  10 - p. 1462-1477 , 2018
Link: https://doi.org/10.1109/..
 
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4

SyRA: Early System Reliability Analysis for Cross-layer Sof..:

Vallero, Alessandro ; Savino, Alessandro ; Chatzidimitriou, Athanasios...
info:eu-repo/semantics/altIdentifier/wos/WOS:000464129300011.  , 2019
Link: http://hdl.handle.net/11..
 
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5

Securing Soft IP Cores in FPGA based Reconfigurable Mobile ..:

Carelli, Alberto ; Basile, Cataldo ; Savino, Alessandro..
http://arxiv.org/abs/1912.00696.  , 2019
Link: http://arxiv.org/abs/191..
 
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6

Performance monitor counters: Interplay between safety and ..:

Carelli, Alberto ; Vallero, Alessandro ; Di Carlo, Stefano
info:eu-repo/semantics/altIdentifier/wos/WOS:000460681900009.  , 2019
Link: http://hdl.handle.net/11..
 
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7

SyRA: early system reliability analysis for cross-layer sof..:

Vallero, Alessandro ; Savino, Alessandro ; Chatzidimitriou, Athanansios...
https://ieeexplore.ieee.org/document/8580414.  , 2018
Link: http://hdl.handle.net/21..
 
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8

SyRA: early system reliability analysis for cross-layer sof..:

Vallero, Alessandro ; Savino, Alessandro ; Chatzidimitriou, Athanansios...
https://ieeexplore.ieee.org/document/8580414.  , 2018
Link: http://hdl.handle.net/21..
 
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9

Shielding Performance Monitor Counters: A double edged weap..:

Carelli, Alberto ; Vallero, Alessandro ; Di Carlo, Stefano
info:eu-repo/semantics/altIdentifier/isbn/9781538659922.  , 2018
Link: http://hdl.handle.net/11..
 
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10

ReDO: Cross-Layer Multi-Objective Design-Exploration Framew..:

Savino, Alessandro ; Vallero, Alessandro ; Di Carlo, Stefano
info:eu-repo/semantics/altIdentifier/wos/WOS:000444003700007.  , 2018
Link: http://hdl.handle.net/11..
 
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11

Trading-off reliability and performance in FPGA-based recon..:

Vallero, Alessandro ; Carelli, Alberto ; Di Carlo, Stefano
info:eu-repo/semantics/altIdentifier/isbn/9781538652916.  , 2018
Link: http://hdl.handle.net/11..
 
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12

Multi-faceted microarchitecture level reliability character..:

Vallero, Alessandro ; Tselonis, Sotiris ; Gizopoulos, Dimitris.
info:eu-repo/semantics/altIdentifier/isbn/9781538637746.  , 2018
Link: http://hdl.handle.net/11..
 
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13

Securing bitstream integrity, confidentiality and authentic..:

Carelli, Alberto ; Cristofanini, Carlo Alberto ; VALLERO, ALESSANDRO...
info:eu-repo/semantics/altIdentifier/isbn/9781538622049.  , 2018
Link: http://hdl.handle.net/11..
 
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14

Cross layer reliability estimation for digital systems:

VALLERO, ALESSANDRO
numberofpages:199.  , 2017
Link: http://hdl.handle.net/11..
 
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15

Microarchitecture level reliability comparison of modern GP..:

VALLERO, ALESSANDRO ; DI CARLO, STEFANO ; Tselonis, Sotiris.
info:eu-repo/semantics/altIdentifier/isbn/9781538638897.  , 2017
Link: http://hdl.handle.net/11..
 
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