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Vudadha, Chetan Kumar
15  Ergebnisse:
Personensuche X
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1

PDCCH Signaling Constrained Mean SNR-Based Resource Allocat..:

, In: 2023 IEEE 16th Malaysia International Conference on Communication (MICC),
Wali, Prashant K. ; Kamath, Gopal Krishna ; Vudadha, Chetan Kumar - p. 113-118 , 2023
Link: https://doi.org/10.1109/..
 
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2

Low Power and High Speed Comparator Design in Quantum-dot C..:

, In: 2023 International Conference on Modeling, Simulation & Intelligent Computing (MoSICom),
Khan, Anas ; Vudadha, Chetan Kumar - p. 19-23 , 2023
Link: https://doi.org/10.1109/..
 
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3

Evaluation of x86 and ARM architectures using compute-inten..:

, In: 2022 IEEE International Symposium on Smart Electronic Systems (iSES),
Bharadwaj, S Vignesh ; Vudadha, Chetan Kumar - p. 586-589 , 2022
Link: https://doi.org/10.1109/..
 
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4

Design of a Ternary Logic Processor Using CNTFET Technology:

Gadgil, Sharvani ; Sandesh, Goli Naga ; Vudadha, Chetan
Circuits, Systems, and Signal Processing.  , 2024
Link: https://doi.org/10.1007/..
 
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5

Design of CNFET-based Ternary Conditional Sum Adders using ..:

, In: 2024 IEEE International Symposium on Circuits and Systems (ISCAS),
Vudadha, Chetan - p. 1-5 , 2024
Link: https://doi.org/10.1109/..
 
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6

Power efficient designs of CNTFET-based ternary SRAM:

Gadgil, Sharvani ; Sandesh, Goli Naga ; Vudadha, Chetan
Microelectronics Journal.  139 (2023)  - p. 105884 , 2023
Link: https://doi.org/10.1016/..
 
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7

An Approximate Full-Adder to Eliminate Carry Propagation in..:

, In: 2023 International Conference on Computer, Electronics & Electrical Engineering & their Applications (IC2E3),
Sudheshna, Bingumalla ; Vudadha, Chetan ; Wali, Prashant. - p. 1-6 , 2023
Link: https://doi.org/10.1109/..
 
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8

Design of CNTFET-based Ternary Logic circuits using Low pow..:

, In: 2022 IEEE International Symposium on Smart Electronic Systems (iSES),
T, Siddharth ; Gadgil, Sharvani ; Vudadha, Chetan - p. 142-147 , 2022
Link: https://doi.org/10.1109/..
 
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9

Novel Design Methodologies for CNFET-Based Ternary Sequenti..:

Gadgil, Sharvani ; Vudadha, Chetan
IEEE Transactions on Nanotechnology.  21 (2022)  - p. 289-298 , 2022
Link: https://doi.org/10.1109/..
 
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10

Optimization of Reversible Circuits Using Gate Pair Classif..:

Sai Phaneendra, P. ; Vudadha, Chetan ; Srinivas, M. B.
SN Computer Science.  3 (2021)  1 - p. , 2021
Link: https://doi.org/10.1007/..
 
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11

A Novel Low Power Ternary Multiplier Design using CNFETs:

, In: 2020 33rd International Conference on VLSI Design and 2020 19th International Conference on Embedded Systems (VLSID),
Sirugudi, Harita ; Gadgil, Sharvani ; Vudadha, Chetan - p. 25-30 , 2020
Link: https://doi.org/10.1109/..
 
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12

FILA: Fault-Model for Interconnection Links in Application-..:

, In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS),
Bhanu, P. Veda ; Vudadha, Chetan ; Soumya, J. - p. 1-5 , 2020
Link: https://doi.org/10.1109/..
 
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13

Design of Area Optimised, Energy Efficient Quaternary Circu..:

, In: 2019 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS),
Patel, Poojan ; Doddapaneni, Nikita ; Gadgil, Sharvani. - p. 280-283 , 2019
Link: https://doi.org/10.1109/..
 
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14

Energy efficient design of CNFET-based multi-digit ternary ..:

Vudadha, Chetan ; Parlapalli, Sai Phaneendra ; Srinivas, M.B.
Microelectronics Journal.  75 (2018)  - p. 75-86 , 2018
Link: https://doi.org/10.1016/..
 
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15

CNFET based ternary magnitude comparator:

, In: 2012 International Symposium on Communications and Information Technologies (ISCIT),
Vudadha, Chetan ; Sai, Phaneendra P. ; Sreehari, V.. - p. 942-946 , 2012
Link: https://doi.org/10.1109/..
 
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