Jimenez, Marc
49  results:
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1

Practically Tackling Memory Bottlenecks of Graph-Processing..:

, In: 2024 IEEE International Parallel and Distributed Processing Symposium (IPDPS),
 
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3

Exploring Preferences in Human-Robot Navigation Plan Propos..:

, In: Companion of the 2024 ACM/IEEE International Conference on Human-Robot Interaction,
 
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4

A Two Level Neural Approach Combining Off-Chip Prediction w..:

, In: 2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA),
 
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6

Sargantana: An Academic SoC RISC-V Processor in 22nm FDSOI ..:

, In: 2023 38th Conference on Design of Circuits and Integrated Systems (DCIS),
Doblas, Max ; Candon, Gerard ; Carril, Xavier... - p. 1-6 , 2023
 
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7

DVINO: A RISC-V Vector Processor Implemented in 65nm Techno..:

, In: 2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS),
 
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8

VR/AR Case Studies:

, In: Virtual and Augmented Reality (VR/AR),
Doerner, Ralf ; Tesch, Alexander ; Hildebrand, Axel... - p. 331-369 , 2022
 
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9

Page Size Aware Cache Prefetching:

, In: 2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO),
Vavouliotis, Georgios ; Chacon, Gino ; Alvarez, Lluc... - p. 956-974 , 2022
 
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10

From Bad Leadership to Responsible Leadership: The Revoluti..:

, In: Debating Bad Leadership; Palgrave Debates in Business and Management,
 
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11

Morrigan: A Composite Instruction TLB Prefetcher:

, In: MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture,
Vavouliotis, Georgios ; Alvarez, Lluc ; Grot, Boris.. - p. 1138-1153 , 2021
 
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12

Exploiting page table locality for agile TLB prefetching:

, In: Proceedings of the 48th Annual International Symposium on Computer Architecture,
 
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13

Human-Robot Collaborative Multi-Agent Path Planning using M..:

, In: 2021 IEEE International Conference on Robotics and Automation (ICRA),
Dalmasso, Marc ; Garrell, Anais ; Dominguez, Jose Enrique.. - p. 10133-10138 , 2021
 
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14

Exploiting Page Table Locality for Agile TLB Prefetching:

, In: 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA),
 
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15

Characterizing the impact of last-level cache replacement p..:

, In: 2020 IEEE International Symposium on Workload Characterization (IISWC),
 
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