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Kumar, Ramayya
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1

Formal verification of pipeline conflicts in RISC processor:

, In: Proceedings of the conference on European design automation,
Kumar, Ramayya ; Tahar, Sofiène - p. 284-289 , 1994
Link: https://dl.acm.org/doi/1..
 
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2

A Formalization of a Hierarchical Model for RISC Processors:

, In: Informatik aktuell; Europäischer Informatik Kongreß Architektur von Rechensystemen Euro-ARCH '93,
Tahar, Sofiène ; Kumar, Ramayya - p. 591-602 , 1993
Link: https://doi.org/10.1007/..
 
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3

Verification of synthesized circuits at register transfer l..:

, In: Proceedings of the conference on European design automation,
Feldbusch, Fridtjof ; Kumar, Ramayya - p. 22-26 , 1991
Link: https://dl.acm.org/doi/1..
 
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4

An automated data path synthesizer for a canonic structure,..:

, In: Proceedings of the 22nd ACM/IEEE Design Automation Conference,
Ramayya, Kumar ; Kumar, Anshul ; Prasad, Surendra - p. 381-387 , 1985
Link: https://dl.acm.org/doi/1..
 
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