Micheli, Eleonora
13  results:
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1

Algebraic and Boolean Optimization Methods for AQFP Superco..:

, In: Proceedings of the 26th Asia and South Pacific Design Automation Conference,
Testa, Eleonora ; Lee, Siang-Yun ; Riener, Heinz. - p. 779-785 , 2021
 
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2

A logic synthesis toolbox for reducing the multiplicative c..:

, In: Proceedings of the 23rd Conference on Design, Automation and Test in Europe,
Testa, Eleonora ; Soeken, Mathias ; Riener, Heinz.. - p. 568-573 , 2020
 
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3

SAT-sweeping enhanced for logic synthesis:

, In: Proceedings of the 57th ACM/EDAC/IEEE Design Automation Conference,
 
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4

A Logic Synthesis Toolbox for Reducing the Multiplicative C..:

, In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE),
Testa, Eleonora ; Soeken, Mathias ; Riener, Heinz.. - p. 568-573 , 2020
 
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5

SAT-Sweeping Enhanced for Logic Synthesis:

, In: 2020 57th ACM/IEEE Design Automation Conference (DAC),
 
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6

Multiplier architectures : challenges and opportunities ..:

, In: Proceedings of the 23rd Conference on Design, Automation and Test in Europe,
 
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7

Multiplier Architectures: Challenges and Opportunities with..:

, In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE),
 
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8

Scalable Generic Logic Synthesis : One Approach to Rule ..:

, In: Proceedings of the 56th Annual Design Automation Conference 2019,
 
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9

Reducing the Multiplicative Complexity in Logic Networks fo..:

, In: Proceedings of the 56th Annual Design Automation Conference 2019,
 
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10

Combining Memory and Non-linearity in Echo State Networks:

, In: Artificial Neural Networks and Machine Learning – ICANN 2018; Lecture Notes in Computer Science,
 
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11

Majority logic synthesis:

, In: Proceedings of the International Conference on Computer-Aided Design,
 
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12

Size Optimization of MIGs with an Application to QCA and ST..:

, In: Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures,
Riener, Heinz ; Testa, Eleonora ; Amaru, Luca.. - p. 157-162 , 2018
 
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13

Classifying Functions with Exact Synthesis:

, In: 2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL),
 
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