Panda, Preeti Ranjan
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1

Education Abstract: Thermal Challenges and Mitigation in 3D..:

, In: Proceedings of the 2023 International Conference on Hardware/Software Codesign and System Synthesis,
 
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2

Techniques for Debug of Low Power SoCs:

, In: 2019 20th International Workshop on Microprocessor/SoC Test, Security and Verification (MTV),
Menon, Sankaran ; Prudvi, Chinna ; Kuehnis, Rolf... - p. 45-49 , 2019
 
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3

DHOOM : Reusing Design-for-Debug Hardware for Online Mon..:

, In: Proceedings of the 56th Annual Design Automation Conference 2019,
 
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4

Debug Data Reduction Techniques:

, In: Post-Silicon Validation and Debug,
Chandran, Sandeep ; Panda, Preeti Ranjan - p. 211-229 , 2018
 
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5

Memory Architectures:

, In: Handbook of Hardware/Software Codesign,
Panda, Preeti Ranjan - p. 411-441 , 2017
 
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6

Energy efficient FFT implementation through stage skipping ..:

, In: Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis,
 
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7

Energy efficient data flow transformation for Givens Rotati..:

, In: 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE),
 
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8

Energy optimization in Android applications through wakeloc..:

, In: 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE),
 
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9

High level energy modeling of controller logic in data cach..:

, In: Proceedings of the 24th edition of the great lakes symposium on VLSI,
 
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10

Energy optimization in android applications through wakeloc..:

, In: Proceedings of the conference on Design, Automation & Test in Europe,
 
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11

Energy efficient data flow transformation for givens rotati..:

, In: Proceedings of the conference on Design, Automation & Test in Europe,
 
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12

Space sensitive cache dumping for post-silicon validation:

, In: Proceedings of the Conference on Design, Automation and Test in Europe,
 
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13

SPM-Sieve : a framework for assisting data partitioning ..:

, In: Proceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems,
 
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14

Integrating software caches with scratch pad memory:

, In: Proceedings of the 2012 international conference on Compilers, architectures and synthesis for embedded systems,
 
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15

Exploiting temporal decoupling to accelerate trace-driven N..:

, In: Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis,
 
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