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Tawada, Masashi
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1

An Ising-Machine-Based Solver of Vehicle Routing Problem Wi..:

Bao, Siya ; Tawada, Masashi ; Tanaka, Shu.
IEEE Transactions on Consumer Electronics.  70 (2024)  1 - p. 445-459 , 2024
Link: https://doi.org/10.1109/..
 
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2

An Efficient Combined Bit-Width Reducing Method for Ising M..:

YACHI, Yuta ; TAWADA, Masashi ; TOGAWA, Nozomu
IEICE Transactions on Information and Systems.  E106.D (2023)  4 - p. 495-508 , 2023
Link: https://doi.org/10.1587/..
 
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3

Hybrid Annealing Method Based on subQUBO Model Extraction W..:

Atobe, Yuta ; Tawada, Masashi ; Togawa, Nozomu
IEEE Transactions on Computers.  71 (2022)  10 - p. 2606-2619 , 2022
Link: https://doi.org/10.1109/..
 
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4

How to Reduce the Bit-Width of an Ising Model by Adding Aux..:

Oku, Daisuke ; Tawada, Masashi ; Tanaka, Shu.
IEEE Transactions on Computers.  71 (2022)  1 - p. 223-234 , 2022
Link: https://doi.org/10.1109/..
 
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5

Mapping Induced Subgraph Isomorphism Problems to Ising Mode..:

YOSHIMURA, Natsuhito ; TAWADA, Masashi ; TANAKA, Shu...
IEICE Transactions on Information and Systems.  E104.D (2021)  4 - p. 481-489 , 2021
Link: https://doi.org/10.1587/..
 
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6

Scalable Stochastic Number Duplicators for Accuracy-flexibl..:

Ishikawa, Ryota ; Tawada, Masashi ; Yanagisawa, Masao.
IPSJ Transactions on System LSI Design Methodology.  13 (2020)  0 - p. 10-20 , 2020
Link: https://doi.org/10.2197/..
 
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7

Stochastic Number Duplicators Based on Bit Re-Arrangement U..:

ISHIKAWA, Ryota ; TAWADA, Masashi ; YANAGISAWA, Masao.
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences.  E101.A (2018)  7 - p. 1002-1013 , 2018
Link: https://doi.org/10.1587/..
 
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8

A Relaxed Bit-Write-Reducing and Error-Correcting Code for ..:

KOJO, Tatsuro ; TAWADA, Masashi ; YANAGISAWA, Masao.
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences.  E101.A (2018)  7 - p. 1045-1052 , 2018
Link: https://doi.org/10.1587/..
 
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9

A Bit-Write-Reducing and Error-Correcting Code Generation M..:

KOJO, Tatsuro ; TAWADA, Masashi ; YANAGISAWA, Masao.
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences.  E99.A (2016)  12 - p. 2398-2411 , 2016
Link: https://doi.org/10.1587/..
 
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10

Code Generation Limiting Maximum and Minimum Hamming Distan..:

KOJO, Tatsuro ; TAWADA, Masashi ; YANAGISAWA, Masao.
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences.  E98.A (2015)  12 - p. 2484-2493 , 2015
Link: https://doi.org/10.1587/..
 
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11

ECC-Based Bit-Write Reduction Code Generation for Non-Volat..:

TAWADA, Masashi ; KIMURA, Shinji ; YANAGISAWA, Masao.
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences.  E98.A (2015)  12 - p. 2494-2504 , 2015
Link: https://doi.org/10.1587/..
 
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12

A High-Speed Trace-Driven Cache Configuration Simulator for..:

TAWADA, Masashi ; YANAGISAWA, Masao ; TOGAWA, Nozomu
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences.  E96.A (2013)  6 - p. 1283-1292 , 2013
Link: https://doi.org/10.1587/..
 
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13

Speeding-up exact and fast FIFO-based cache configuration s..:

Tawada, Masashi ; Yanagisawa, Masao ; Togawa, Nozomu
IEICE Electronics Express.  8 (2011)  14 - p. 1161-1167 , 2011
Link: https://doi.org/10.1587/..
 
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14

Exact, Fast and Flexible L1 Cache Configuration Simulation ..:

Tawada, Masashi ; Yanagisawa, Masao ; Ohtsuki, Tatsuo.
IPSJ Transactions on System LSI Design Methodology.  4 (2011)  - p. 166-181 , 2011
Link: https://doi.org/10.2197/..
 
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15

Role of endothelial hyaluronan in peritoneal membrane trans..:

Kamiya, Keisuke ; Hatayama, Naoyuki ; Tawada, Mitsuhiro...
Scientific Reports.  14 (2024)  1 - p. , 2024
Link: https://doi.org/10.1038/..
 
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