Cai, Yici
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2

Logic and Layout Aware Level Converter Optimization for Mul..:

GUO, Liangpeng ; CAI, Yici ; ZHOU, Qiang.
http://journals.fcla.edu/ietfec-a/article/view/17652/17318.  , 2008
 
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3

Dummy Fill Aware Buffer Insertion after Layer Assignment Ba..:

JIA, Yanming ; CAI, Yici ; HONG, Xianlong
http://journals.fcla.edu/ietfec-a/article/view/17875/17541.  , 2008
 
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4

Early Stage Power Supply Planning: A Heuristic Method for C..:

WANG, Xiaoyi ; SHI, Jin ; CAI, Yici.
http://journals.fcla.edu/ietfec-a/article/view/17839/17505.  , 2008
 
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5

Low Power Gated Clock Tree Driven Placement:

SHEN, Weixiang ; CAI, Yici ; HONG, Xianlong.
http://journals.fcla.edu/ietfec-a/article/view/17442/17108.  , 2008
 
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6

Stochastic Interconnect Tree Construction Algorithm with Ac..:

WANG, Yibo ; CAI, Yici ; HONG, Xianlong.
http://journals.fcla.edu/ietfec-a/article/view/17106/16772.  , 2007
 
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7

Voltage Island Generation in Cell Based Dual-Vdd Design:

CAI, Yici ; LIU, Bin ; ZHOU, Qiang.
http://journals.fcla.edu/ietfec-a/article/view/17001/16667.  , 2007
 
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8

A Fast Delay Computation for the Hybrid Structured Clock Ne..:

ZOU, Yi ; CAI, Yici ; ZHOU, Qiang..
http://journals.fcla.edu/ietfec-a/article/view/16215/15881.  , 2005
 
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9

Navigating Register Placement for Low Power Clock Network D..:

LU, Yongqiang ; SZE, Chin-Ngai ; HONG, Xianlong...
http://journals.fcla.edu/ietfec-a/article/view/16417/16083.  , 2005
 
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10

Crosstalk and Congestion Driven Layer Assignment Algorithm:

LIU, Bin ; CAI, Yici ; ZHOU, Qiang.
http://journals.fcla.edu/ietfec-a/article/view/16165/15831.  , 2005
 
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