Ajayi, Tutu
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1

Versa: A 36-Core Systolic Multiprocessor With Dynamically R..:

Kim, Sung ; Fayazi, Morteza ; Daftardar, Alhad...
IEEE Journal of Solid-State Circuits.  57 (2022)  4 - p. 986-998 , 2022
 
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2

A Unified Forward Error Correction Accelerator for Multi-Mo..:

, In: Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design,
Yue, Yufan ; Ajayi, Tutu ; Liu, Xueyang... - p. 1-6 , 2022
 
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4

Fully-Autonomous SoC Synthesis Using Customizable Cell-Base..:

, In: VLSI-SoC: Design Trends; IFIP Advances in Information and Communication Technology,
Ajayi, Tutu ; Kamineni, Sumanth ; Fayazi, Morteza... - p. 65-85 , 2021
 
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5

Bridging academic open-source EDA to real-world usability:

, In: Proceedings of the 39th International Conference on Computer-Aided Design,
Rovinski, Austin ; Ajayi, Tutu ; Kim, Minsoo.. - p. 1-7 , 2020
 
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6

An Open-source Framework for Autonomous SoC Design with Ana..:

, In: 2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration (VLSI-SOC),
 
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7

Toward an Open-Source Digital Flow : First Learnings fro..:

, In: Proceedings of the 56th Annual Design Automation Conference 2019,
 
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8

Evaluating Celerity: A 16-nm 695 Giga-RISC-V Instructions/s..:

Rovinski, Austin ; Veluri, Bandhav ; Rao, Anuj...
IEEE Solid-State Circuits Letters.  2 (2019)  12 - p. 289-292 , 2019
 
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