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Alexander Barkalov
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1

Hardware Reduction for FSMs With Extended State Codes:

Barkalov, Alexander ; Titarenko, Larysa ; Mielcarek, Kamil.
IEEE Access.  12 (2024)  - p. 42369-42384 , 2024
Link: https://doi.org/10.1109/..
 
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2

Basic Approaches for Reducing Power Consumption in Finite S..:

Barkalov, Alexander ; Titarenko, Larysa ; Bieganowski, Jacek.
Applied Sciences.  14 (2024)  7 - p. 2693 , 2024
Link: https://doi.org/10.3390/..
 
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3

Improving the Spatial Characteristics of Three-Level LUT-Ba..:

Barkalov, Alexander ; Titarenko, Larysa ; Mazurkiewicz, Małgorzata.
Electronics.  12 (2023)  5 - p. 1133 , 2023
Link: https://doi.org/10.3390/..
 
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4

Solving Load Balancing Problems in Routing and Limiting Tra..:

Barkalov, Alexander ; Lemeshko, Oleksandr ; Yeremenko, Oleksandra..
Applied Sciences.  13 (2023)  17 - p. 9489 , 2023
Link: https://doi.org/10.3390/..
 
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5

Hierarchical Queue Management Priority and Balancing Based ..:

Lemeshko, Oleksandr ; Yeremenko, Oleksandra ; Titarenko, Larysa.
Electronics.  12 (2023)  3 - p. 675 , 2023
Link: https://doi.org/10.3390/..
 
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6

Optimization of a Mealy Automaton Circuit in a Mixed Elemen..:

Barkalov, Alexander ; Titarenko, Larysa ; Golovin, Oleksandr.
Cybernetics and Computer Technologies.  , 2023
Link: https://doi.org/10.34229..
 
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7

Improving Characteristics of FPGA-Based FSMs Representing S..:

Barkalov, Alexander ; Titarenko, Larysa ; Krzywicki, Kazimierz.
Applied Sciences.  13 (2023)  18 - p. 10200 , 2023
Link: https://doi.org/10.3390/..
 
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8

Improving Characteristics of LUT-Based Three-Block Mealy FS..:

Barkalov, Alexander ; Titarenko, Larysa ; Krzywicki, Kazimierz.
Electronics.  11 (2022)  6 - p. 950 , 2022
Link: https://doi.org/10.3390/..
 
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9

Reducing Hardware in LUT-Based Mealy FSMs with Encoded Coll..:

Barkalov, Alexander ; Titarenko, Larysa ; Mazurkiewicz, Małgorzata
Electronics.  11 (2022)  20 - p. 3389 , 2022
Link: https://doi.org/10.3390/..
 
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10

Logic Synthesis for VLSI-Based Combined Finite State Machin.. 

Lecture Notes in Electrical Engineering, 922
Barkalov, Alexander ; Titarenko, Larysa ; Mielcarek, Kamil.. - 1st ed. 2022 . , 2022
Link: https://doi.org/10.1007/..
 
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11

ASIC-based Synthesis of CFSMs:

, In: Lecture Notes in Electrical Engineering; Logic Synthesis for VLSI-Based Combined Finite State Machines,
Barkalov, Alexander ; Titarenko, Larysa ; Mielcarek, Kamil.. - p. 77-110 , 2022
Link: https://doi.org/10.1007/..
 
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12

Heterogeneous CPLD-based Synthesis of CFSMs:

, In: Lecture Notes in Electrical Engineering; Logic Synthesis for VLSI-Based Combined Finite State Machines,
Barkalov, Alexander ; Titarenko, Larysa ; Mielcarek, Kamil.. - p. 179-214 , 2022
Link: https://doi.org/10.1007/..
 
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13

Homogenous CPLD-Based Synthesis of CFSMs:

, In: Lecture Notes in Electrical Engineering; Logic Synthesis for VLSI-Based Combined Finite State Machines,
Barkalov, Alexander ; Titarenko, Larysa ; Mielcarek, Kamil.. - p. 145-178 , 2022
Link: https://doi.org/10.1007/..
 
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14

CPLD-Based Synthesis with Transformation of State Codes:

, In: Lecture Notes in Electrical Engineering; Logic Synthesis for VLSI-Based Combined Finite State Machines,
Barkalov, Alexander ; Titarenko, Larysa ; Mielcarek, Kamil.. - p. 215-248 , 2022
Link: https://doi.org/10.1007/..
 
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15

Reducing LUT Count for Mealy FSMs With Transformation of St..:

Barkalov, Alexander A. ; Titarenko, Larysa ; Mielcarek, Kamil
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.  41 (2022)  5 - p. 1400-1411 , 2022
Link: https://doi.org/10.1109/..
 
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