Bae, Seung-Jun
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1

Analysis of the Effects of Power Partitioning in LPDDR4x Pa..:

, In: 2024 IEEE 28th Workshop on Signal and Power Integrity (SPI),
Kim, Jun-Bae ; Kim, Taeho ; Yoon, Chang Soo... - p. 1-4 , 2024
 
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2

13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic ..:

, In: 2024 IEEE International Solid-State Circuits Conference (ISSCC),
Choi, Ikjoon ; Hong, Seunghwan ; Kim, Kihyun... - p. 234-236 , 2024
 
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4

Near-Field EMI Analysis of LPDDR5 DRAM at idle mode:

, In: 2023 IEEE Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMC+SIPI),
Kim, Jun-Bae ; Kwon, Chang Ki ; Kim, Taeho... - p. 311-314 , 2023
 
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5

A 1.01V 8.5Gb/s/pin 16Gb LPDDR5x SDRAM with Self-Pre-Emphas..:

, In: 2023 IEEE Asian Solid-State Circuits Conference (A-SSCC),
Ahn, Hyun-A ; Sung, Yoo-Chang ; Kim, Yong-Hun... - p. 1-4 , 2023
 
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6

Contributors:

, In: Semiconductor Memories and Systems,
Bae, Seung-Jun ; Bez, Roberto ; Cappelletti, Paolo... - p. xi-xii , 2022
 
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7

DRAM circuit and process technology:

, In: Semiconductor Memories and Systems,
 
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8

Session 16 Overview: Computation in Memory:

, In: 2021 IEEE International Solid-State Circuits Conference (ISSCC),
Chang, Meng-Fan ; Huang, Ru ; Bae, Seung-Jun - p. 244-245 , 2021
 
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9

22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Ar..:

, In: 2020 IEEE International Solid- State Circuits Conference - (ISSCC),
Chi, Hyung-Joon ; Lee, Chang-Kyo ; Park, Junghwan... - p. 382-384 , 2020
 
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10

An 8-bit 2.8 GS/s Flash ADC with Time-based Offset Calibrat..:

, In: ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC),
Yang, Xi ; Bae, Seung-Jun ; Lee, Hae-Seung - p. 305-308 , 2019
 
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11

Session 12 overview: DRAM: Memory subcommittee:

, In: 2018 IEEE International Solid-State Circuits Conference - (ISSCC),
 
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12

F5: Wireline transceivers for Mega Data Centers: 50Gb/s and..:

, In: 2017 IEEE International Solid-State Circuits Conference (ISSCC),
Frans, Yohan ; Fujimori, Ichiro ; Bae, Seung-Jun... - p. 512-514 , 2017
 
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13

Session 23 overview: DRAM, MRAM & DRAM interfaces:

, In: 2017 IEEE International Solid-State Circuits Conference (ISSCC),
 
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14

An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Po..:

, In: 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers,
Ihm, Jeong-Don ; Bang, Sam-Young ; Lee, Mi-Jin... - p. None , 2007
 
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