I agree that this site is using cookies. You can find further informations here.
X
Berkelaar, Michel
12  results:
Search for persons X
?
1

Session details: Logic synthesis techniques:

, In: Proceedings of the Conference on Design, Automation and Test in Europe,
Berkelaar, Michel ; Cortadella, Jordi , 2013
Link: https://dl.acm.org/doi/1..
 
?
2

Transistor-level gate model based statistical timing analys..:

, In: Proceedings of the Conference on Design, Automation and Test in Europe,
Tang, Qin ; Zjajo, Amir ; Berkelaar, Michel. - p. 917-922 , 2012
Link: https://dl.acm.org/doi/1..
 
?
3

RDE-based transistor-level gate simulation for statistical ..:

, In: Proceedings of the 47th Design Automation Conference,
Tang, Qin ; Zjajo, Amir ; Berkelaar, Michel. - p. 787-792 , 2010
Link: https://dl.acm.org/doi/1..
 
?
4

Polarized observability don't cares:

, In: Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design,
Arts, Harm ; Berkelaar, Michel ; van Eijk, C. A. J. - p. 626-631 , 1997
Link: https://dl.acm.org/doi/1..
 
?
5

Efficient orthonormality testing for synthesis with pass-tr..:

, In: Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design,
Berkelaar, Michel ; van Ginneken, Lukas P. P. P. - p. 256-263 , 1995
Link: https://dl.acm.org/doi/1..
 
?
6

Computing the entire active area/power consumption versus d..:

, In: Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design,
Berkelaar, Michel R. C. M. ; Buurman, Pim H. W. ; Jess, Jochen A. G. - p. 474-480 , 1994
Link: https://dl.acm.org/doi/1..
 
?
7

Gate sizing in MOS digital circuits with linear programming:

, In: Proceedings of the conference on European design automation,
Berkelaar, Michel R. C. M. ; Jess, Jochen A. G. - p. 217-221 , 1990
Link: https://dl.acm.org/doi/1..
 
?
8

Computing observability don't cares efficiently through pol..:

Arts, HMAM ; Berkelaar, MRCM Michel ; Eijk, CAJ Koen van
ISSN:0278-0070.  , 1998
Link: http://repository.tue.nl..
 
?
9

Improved state assignment for burst mode finite state machi..:

Rutten, JWJM Jeroen ; Berkelaar, MRCM Michel , 1997
Link: http://repository.tue.nl..
 
?
10

Computing the entire area/power consumption versus delay tr..:

Berkelaar, MRCM Michel ; Buurman, HW Pim ; Jess, JAG Jochen
ISSN:0278-0070.  , 1996
Link: http://repository.tue.nl..
 
?
11

Area-power-delay trade-off in logic synthesis:

Berkelaar, MRCM Michel , 1992
Link: http://repository.tue.nl..
 
?
12

Technology mapping from boolean expressions to standard cel..:

Berkelaar, MRCM Michel ; Theeuwen, JFM Frans , 1987
Link: http://repository.tue.nl..
 
1-12