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Candon, Gerard
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1

Sargantana: An Academic SoC RISC-V Processor in 22nm FDSOI ..:

, In: 2023 38th Conference on Design of Circuits and Integrated Systems (DCIS),
Doblas, Max ; Candon, Gerard ; Carril, Xavier... - p. 1-6 , 2023
Link: https://doi.org/10.1109/..
 
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2

DVINO: A RISC-V Vector Processor Implemented in 65nm Techno..:

, In: 2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS),
Cabo, Guillem ; Candon, Gerard ; Carril, Xavier... - p. 1-6 , 2022
Link: https://doi.org/10.1109/..
 
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3

Sargantana: A 1 GHz+ In-Order RISC-V Processor with SIMD Ve..:

, In: 2022 25th Euromicro Conference on Digital System Design (DSD),
Soria-Pardos, Victor ; Doblas, Max ; Lopez-Paradis, Guillem... - p. 254-261 , 2022
Link: https://doi.org/10.1109/..
 
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4

DVINO: A RISC-V vector processor implemented in 65nm techno..:

Cabo Pitarch, Guillem ; Candon, Gerard ; Carril, Xavier...
https://ieeexplore.ieee.org/document/9970128.  , 2022
Link: http://hdl.handle.net/21..
 
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5

Sargantana: A 1 GHz+ in-order RISC-V processor with SIMD ve..:

Soria Pardos, Víctor ; Doblas Font, Max ; López Paradís, Guillem...
https://ieeexplore.ieee.org/document/9996608.  , 2022
Link: http://hdl.handle.net/21..
 
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6

Implementación de un procesador RISC-V en una FPGA:

Candón Arenas, Gerard
http://hdl.handle.net/2117/329221.  , 2020
Link: http://hdl.handle.net/21..
 
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