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Chinnery, David
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1

Task-Based Parallel Programming for Gate Sizing:

Mangiras, Dimitrios ; Chinnery, David ; Dimitrakopoulos, Giorgos
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.  42 (2023)  4 - p. 1309-1322 , 2023
Link: https://doi.org/10.1109/..
 
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2

Proceedings of the 2023 International Symposium on Physical..:

Chinnery, David ; Hui-Ru Jiang, Iris , 2023
Link: https://dl.acm.org/doi/1..
 
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3

EDA for Domain Specific Computing : An Introduction for ..:

, In: Proceedings of the 2023 International Symposium on Physical Design,
Jiang, Iris Hui-Ru ; Chinnery, David - p. 205 ff. , 2023
Link: https://dl.acm.org/doi/1..
 
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4

Introduction to the Special Section on Advances in Physical..:

Jiang, Iris Hui-Ru ; Chinnery, David ; Posser, Gracieli.
ACM Transactions on Design Automation of Electronic Systems.  28 (2023)  5 - p. 1-3 , 2023
Link: https://doi.org/10.1145/..
 
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5

Session details: Session 17: ISPD 2022 Contest Results and ..:

, In: Proceedings of the 2022 International Symposium on Physical Design,
Chinnery, David , 2022
Link: https://dl.acm.org/doi/1..
 
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6

Integrating LR Gate Sizing in an Industrial Place-and-Route..:

, In: Proceedings of the 2022 International Symposium on Physical Design,
Chinnery, David ; Sharma, Ankur - p. 39-48 , 2022
Link: https://dl.acm.org/doi/1..
 
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7

Session details: Advanced VLSI Routing and Layout Learning:

, In: Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design,
Chow, Wing-Kai ; Chinnery, David , 2022
Link: https://dl.acm.org/doi/1..
 
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8

Session details: Session 4: Circuit Design and Security:

, In: Proceedings of the 2020 International Symposium on Physical Design,
Chinnery, David , 2020
Link: https://dl.acm.org/doi/1..
 
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9

Design Optimization by Fine-grained Interleaving of Local N..:

, In: Proceedings of the 2020 International Symposium on Physical Design,
Stefanidis, Apostolos ; Mangiras, Dimitrios ; Nicopoulos, Chrysostomos.. - p. 87-94 , 2020
Link: https://dl.acm.org/doi/1..
 
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10

Session details: Detailed Routing Contest Results:

, In: Proceedings of the 2019 International Symposium on Physical Design,
Chinnery, David , 2019
Link: https://dl.acm.org/doi/1..
 
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11

Timing-Driven and Placement-Aware Multibit Register Composi..:

Seitanidis, Ioannis ; Dimitrakopoulos, Giorgos ; Mattheakis, Pavlos M...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.  38 (2019)  8 - p. 1501-1514 , 2019
Link: https://doi.org/10.1109/..
 
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12

Lagrangian Relaxation Based Gate Sizing With Clock Skew Sch..:

, In: Proceedings of the 2019 International Symposium on Physical Design,
Sharma, Ankur ; Chinnery, David ; Chu, Chris - p. 129-137 , 2019
Link: https://dl.acm.org/doi/1..
 
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13

Timing Driven Incremental Multi-Bit Register Composition Us..:

, In: Proceedings of the 54th Annual Design Automation Conference 2017,
Seitanidis, Ioannis ; Dimitrakopoulos, Giorgos ; Mattheakis, Pavlos.. - p. 1-6 , 2017
Link: https://dl.acm.org/doi/1..
 
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14

Rapid gate sizing with fewer iterations of lagrangian relax..:

, In: Proceedings of the 36th International Conference on Computer-Aided Design,
Sharma, Ankur ; Chinnery, David ; Dhamdhere, Shrirang. - p. 337-343 , 2017
Link: https://dl.acm.org/doi/1..
 
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15

Session details: 3D Circuits:

, In: Proceedings of the 2016 on International Symposium on Physical Design,
Chinnery, David , 2016
Link: https://dl.acm.org/doi/1..
 
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