Chiou-Yng Lee
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1

Reliable Concurrent Error Detection Architectures for Exten..:

Mozaffari-Kermani, Mehran ; Azarderakhsh, Reza ; Chiou-Yng Lee.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  22 (2014)  5 - p. 995-1003 , 2014
 
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2

Concurrent Error Detection in Bit-Serial Normal Basis Multi..:

Chiou-Yng Lee ; Meher, Pramod Kumar ; Patra, Jagdish Chandra
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  18 (2010)  8 - p. 1234-1238 , 2010
 
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3

Social network learning based on Blue-Red Trees inference a..:

, In: IET International Conference on Frontier Computing. Theory, Technologies and Applications,
Yung-Hui Chen ; Yen-Da Chen ; Chiou-Yng Lee... - p. 312-317 , 2010
 
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5

Hardware Implementation of High-Performance Polynomial Mult..:

, In: 2022 IEEE International Symposium on Circuits and Systems (ISCAS),
Tu, Yazheng ; He, Pengzhou ; Lee, Chiou-Yng.. - p. 1160-1164 , 2022
 
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6

Efficient Subquadratic Space Complexity Digit-Serial Multip..:

, In: 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC),
Lee, Chiou-Yng ; Xie, Jiafeng - p. 253-258 , 2020
 
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7

Efficient Scalable Three Operand Multiplier Over GF(2^m) Ba..:

, In: 2019 IEEE 37th International Conference on Computer Design (ICCD),
Lee, Chiou-Yng ; Xie, Jiafeng - p. 29-37 , 2019
 
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8

Novel Systolization of Subquadratic Space Complexity Multip..:

Pan, Jeng-Shyang ; Lee, Chiou-Yng ; Sghaier, Anissa..
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  27 (2019)  7 - p. 1614-1622 , 2019
 
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9

Novel Bit-Parallel and Digit-Serial Systolic Finite Field M..:

Xie, Jiafeng ; Lee, Chiou-Yng ; Meher, Pramod Kumar.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  27 (2019)  9 - p. 2119-2130 , 2019
 
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10

Embracing Systolic : Super Systolization of Large-Scale ..:

, In: Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays,
Xie, Jiafeng ; Lee, Chiou-Yng - p. 187 ff. , 2019
 
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11

LSM : Novel Low-Complexity Unified Systolic Multiplier o..:

, In: Proceedings of the 2019 Great Lakes Symposium on VLSI,
Xie, Jiafeng ; Lee, Chiou-Yng - p. 343-346 , 2019
 
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12

Low Register-Complexity Systolic Digit-Serial Multiplier Ov..:

Xie, Jiafeng ; Meher, Pramod Kumar ; Zhou, Xiaojun.
IEEE Transactions on Multi-Scale Computing Systems.  4 (2018)  4 - p. 773-783 , 2018
 
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13

Low-Complexity Digit-Serial Multiplier Over $GF(2^{m})$ Bas..:

Lee, Chiou-Yng ; Meher, Pramod Kumar ; Fan, Chia-Chen.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  25 (2017)  2 - p. 735-746 , 2017
 
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14

Area-Delay Efficient Digit-Serial Multiplier Based on$k$-Pa..:

Lee, Chiou-Yng ; Meher, Pramod Kumar ; Liu, Chung-Hsin
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  24 (2016)  7 - p. 2413-2425 , 2016
 
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15

Systolic Gaussian Normal Basis Multiplier Architectures Sui..:

Azarderakhsh, Reza ; Kermani, Mehran Mozaffari ; Bayat-Sarmadi, Siavash.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  23 (2015)  9 - p. 1969-1972 , 2015
 
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