Chua-Chin Wang
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1

A Voltage Monitoring IC With HV Multiplexer and HV Transcei..:

Chih-Lin Chen ; Deng-Shian Wang ; Jie-Jyun Li.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  23 (2015)  2 - p. 244-253 , 2015
 
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2

A power-aware 2-dimensional bypassing multiplier using cell..:

, In: 2008 IEEE International Symposium on Circuits and Systems (ISCAS),
 
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3

Power-saving nano-scale DRAMs with an adaptive refreshing c..:

, In: 2008 IEEE International Symposium on Circuits and Systems (ISCAS),
Tung-Han Tsai ; Chin-Lin Chen ; Ching-Li Lee. - p. None , 2008
 
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4

A Low Power High-Speed 8-Bit Pipelining CLA Design Using Du..:

Chua-Chin Wang ; Chi-Chun Huang ; Ching-Li Lee.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  16 (2008)  5 - p. 594-598 , 2008
 
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5

A mini-invasive multi-function bladder urine pressure measu..:

, In: 2008 IEEE International Symposium on Circuits and Systems (ISCAS),
Chua-Chin Wang ; Chi-Chun Huang ; Jun-Han Wu... - p. None , 2008
 
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6

A temperature-insensitive self-recharging circuitry used in..:

Chua-Chin Wang ; Yih-Long Tseng ; Chih-Chiang Chiu
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  13 (2005)  3 - p. 405-408 , 2005
 
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7

A multiparameter implantable microstimulator SOC:

Chua-Chin Wang ; Tzung-Je Lee ; Yu-Tzu Hsiao...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  13 (2005)  12 - p. 1399-1402 , 2005
 
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8

A 13-bit resolution ROM-less direct digital frequency synth..:

Chua-Chin Wang ; Yih-Long Tseng ; Hsien-Chih She..
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  12 (2004)  9 - p. 895-900 , 2004
 
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9

A 4-kB 500-MHz 4-T CMOS SRAM using low-V/sub THN/ bitline d..:

Chua-Chin Wang ; Yih-Long Tseng ; Hon-Yuan Leo.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  12 (2004)  9 - p. 901-909 , 2004
 
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10

A 1.2 GHz programmable DLL-based frequency multiplier for w..:

Chua-Chin Wang ; Yih-Long Tseng ; Hsien-Chih She.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  12 (2004)  12 - p. 1377-1381 , 2004
 
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11

An area-saving decoder structure for ROMs:

Chua-Chin Wang ; Ya-Hsin Hsueh ; Ying-Pei Chen
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  11 (2003)  4 - p. 581-589 , 2003
 
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12

Design of a cycle-efficient 64-b/32-b integer divisor using..:

Chua-Chin Wang ; Po-Ming Lee ; Jun-Jie Wang.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  11 (2003)  4 - p. 737-740 , 2003
 
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14

A modified measure for fuzzy subsethood:

Chua-Chin, Wang ; Hon-Son, Don
Information Sciences.  79 (1994)  3-4 - p. 223-232 , 1994
 
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15

A 54.61-GOPS 96.35-mW Digital Logic Accelerator For Underwa..:

, In: 2024 IEEE 6th International Conference on AI Circuits and Systems (AICAS),
Wang, Chua-Chin ; Luo, Shih-Heng ; Wu, Hsin-Che... - p. 85-89 , 2024
 
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