Chung, Yung-Hui
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1

A 10b 400MS/s 2x-Time-Interleaved 2-Then-1b/Cycle SAR ADC i..:

, In: 2024 IEEE International Symposium on Circuits and Systems (ISCAS),
 
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2

A 105-dB SFDR 16-bit SAR ADC with a Window Capacitor Calibr..:

, In: 2024 IEEE International Symposium on Circuits and Systems (ISCAS),
 
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3

A 90-dB DR Discrete-Time Delta-Sigma Modulator for Audio Ap..:

, In: 2023 20th International SoC Design Conference (ISOCC),
 
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4

A 16-Bit Calibration-Free SAR ADC With Binary-Window and Ca..:

Chung, Yung-Hui ; Tien, Chia-Hui ; Zeng, Qi-Feng
IEEE Transactions on Circuits and Systems I: Regular Papers.  69 (2022)  1 - p. 88-99 , 2022
 
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5

A 12-bit 100-kS/s SAR ADC for IoT Applications:

, In: 2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT),
Chung, Yung-Hui ; Zeng, Qi-Feng - p. 1-4 , 2020
 
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6

A 12-bit Domino ADC with a Background Offset Calibration Sc..:

, In: 2019 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS),
Chung, Yung-Hui - p. 9-12 , 2019
 
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7

A 102dB-SFDR 16-bit Calibration-Free SAR ADC in 180-nm CMOS:

, In: 2019 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS),
 
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8

A High-Performance AWG-based Optical WDM Two-SubRing Networ:

, In: 2019 4th International Conference on Intelligent Green Building and Smart Grid (IGBSG),
 
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9

A 12-bit 40-MS/s SAR ADC With a Fast-Binary-Window DAC Swit..:

Chung, Yung-Hui ; Yen, Chia-Wei ; Tsai, Pei-Kang.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  26 (2018)  10 - p. 1989-1998 , 2018
 
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11

An 11-bit 100-MS/s Subranged-SAR ADC in 65-nm CMOS:

Chung, Yung-Hui ; Yen, Chia-Wei
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  25 (2017)  12 - p. 3434-3443 , 2017
 
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12

Nano Devices and Sensors 

De Gruyter eBook-Paket Technik, Informatik
 
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14

A 24- $\mu \text{W}$ 12-bit 1-MS/s SAR ADC With Two-Step De..:

Chung, Yung-Hui ; Yen, Chia-Wei ; Wu, Meng-Hsuan
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  24 (2016)  11 - p. 3334-3344 , 2016
 
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