Clerc, R.
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2

Lowering the Dark Count Rate of SPAD Implemented in CMOS FD..:

, In: 2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS),
 
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Evidence of band bending induced by hole trapping at MAPbI3..:

Chen, Y.-F. ; Tsai, Y.-T. ; Bassani, D. M....
Journal of Materials Chemistry A.  4 (2016)  44 - p. 17529-17536 , 2016
 
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Multi-scale strategy for high-k/metal-gate UTBB-FDSOI devic..:

Nier, O. ; Rideau, D. ; Niquet, Y. M....
Journal of Computational Electronics.  12 (2013)  4 - p. 675-684 , 2013
 
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Characterization and 3D TCAD simulation of NOR-type flash n..:

Zaka, A. ; Singer, J. ; Dornel, E....
Solid-State Electronics.  63 (2011)  1 - p. 158-162 , 2011
 
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HfO2-based gate stacks transport mechanisms and parameter e..:

Coignus, J. ; Leroux, C. ; Clerc, R....
Solid-State Electronics.  54 (2010)  9 - p. 972-978 , 2010
 
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11

Performance and analytical modeling of Metal–Insulator-Meta..:

Ferrier, M. ; Zhang, D. ; Griffin, P....
Solid-State Electronics.  54 (2010)  12 - p. 1525-1531 , 2010
 
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A compact drain current model of short-channel cylindrical ..:

Tsormpatzoglou, A ; Tassis, D H ; Dimitriadis, C A...
Semiconductor Science and Technology.  24 (2009)  7 - p. 075017 , 2009
 
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NANOSIL network of excellence—silicon-based nanostructures ..:

Balestra, F. ; Parker, E. ; Leadley, D....
Materials Science in Semiconductor Processing.  11 (2008)  5-6 - p. 148-159 , 2008
 
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Modeling and optimization of series resistance of planar MI..:

Bajolet, A. ; Clerc, R. ; Pananakakis, G....
Solid-State Electronics.  50 (2006)  7-8 - p. 1244-1251 , 2006
 
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