Deschacht, D.
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1

Physica status solidi 

Volume 71, Number 2: June 16  Physica status solidi ; Volume 71, Number 2, A
Abdel-Maksoud, S ; Abdelmohsen, N ; Abou El Ela, A. H... - Reprint 2021 . , [2022]
 
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2

RLC Crosstalk Calculation with Dissymmetrical Attacks:

, In: 2007 IEEE Workshop on Signal Propagation on Interconnects,
Lorival, J. E. ; Deschacht, D. - p. None , 2007
 
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3

DSM interconnects: importance of inductance effects and cor..:

Deschacht, D.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  14 (2006)  7 - p. 777-779 , 2006
 
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4

On-chip interconnections : impact of adjacent lines on t..:

, In: Proceedings of the 2001 Asia and South Pacific Design Automation Conference,
Deschacht, D. ; Servel, G. - p. 539-544 , 2001
 
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5

Theoretical limits for signal reflections due to inductance..:

, In: Proceedings of the 2000 international workshop on System-level interconnect prediction,
Deschacht, D. ; Servel, G. ; Huret, F... - p. 55-60 , 2000
 
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6

A full-wave analysis of submicronic circuits in the microwa..:

Servel, G. ; Huret, F. ; Paleczny, E...
Microwave and Optical Technology Letters.  23 (1999)  6 - p. 376-380 , 1999
 
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7

A new and accurate interconnection delay time evaluation in..:

, In: Proceedings of the 1995 Asia and South Pacific Design Automation Conference,
Deschacht, D. ; Dabrin, C. - p. 56-es , 1995
 
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8

TVA: A timing verifier with analytic temporal modelling:

Navarro, D. ; Roy, A. ; Robert, M...
Microprocessing and Microprogramming.  32 (1991)  1-5 - p. 637-644 , 1991
 
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9

Formal sizing rules of CMOS circuits:

, In: Proceedings of the conference on European design automation,
Auvergne, D. ; Azemard, N. ; Bonzom, V... - p. 96-100 , 1991
 
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10

Path runner : an accurate and fast timing analyser:

, In: Proceedings of the conference on European design automation,
Deschacht, D. ; Pinede, P. ; Robert, M.. - p. 529-533 , 1990
 
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