Favia, P
211  results:
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1

Nanosheet-based Complementary Field-Effect Transistors (CFE..:

, In: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits),
Mertens, H. ; Hosseini, M. ; Chiarella, T.... - p. 1-2 , 2023
 
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Nanosheet-based Device Architectures with Front/Backside Co..:

, In: 2023 21st International Workshop on Junction Technology (IWJT),
Veloso, A. ; Eneman, G. ; Matagne, P.... - p. 1-5 , 2023
 
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4

Integration of epitaxial monolayer MX₂ channels on 300mm wa..:

, In: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits),
Ghosh, S. ; Smets, Q. ; Banerjee, S.... - p. 1-2 , 2023
 
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5

High performance La-doped HZO based ferroelectric capacitor..:

, In: 2022 International Electron Devices Meeting (IEDM),
Popovici, M.I. ; Bizindavyi, J. ; Favia, P.... - p. 6.4.1-6.4.4 , 2022
 
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7

Innovations in Transistor Architecture and Device Connectiv..:

, In: 2022 International Conference on IC Design and Technology (ICICDT),
Veloso, A. ; Eneman, G. ; De Keersgieter, A.... - p. 51-54 , 2022
 
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8

Monte Carlo Analysis of -Type SiGe-Channel Nanosheet Perfor..:

Bufler, F. M. ; Arimura, H. ; Favia, P....
IEEE Transactions on Electron Devices.  69 (2022)  11 - p. 6384-6387 , 2022
 
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9

High Performance Thermally Resistant FinFETs DRAM Periphera..:

, In: 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits),
Ritzenthaler, R. ; Capogreco, E. ; Dupuy, E.... - p. 306-307 , 2022
 
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10

Low temperature source/drain epitaxy and functional silicid..:

, In: 2022 International Electron Devices Meeting (IEDM),
Porret, C. ; Everaert, J.-L. ; Schaekers, M.... - p. 34.1.1-34.1.4 , 2022
 
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11

Understanding the kinetics of Metal Induced Lateral Crystal..:

, In: 2021 IEEE International Electron Devices Meeting (IEDM),
Ramesh, S. ; Palayam, S. Vadakupudhu ; Ajaykumar, A.... - p. 10.2.1-10.2.4 , 2021
 
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12

Probing the evolution of electrically active defects in dop..:

, In: 2020 IEEE Symposium on VLSI Technology,
Celano, U. ; Chen, Y.-H. ; Minj, A.... - p. 1-2 , 2020
 
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13

Addressing Key Challenges for SiGe-pFin Technologies: Fin I..:

, In: 2020 IEEE Symposium on VLSI Technology,
Arimura, H. ; Capogreco, E. ; Wostyn, K.... - p. 1-2 , 2020
 
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14

Buried Power Rail Integration with Si FinFETs for CMOS Scal..:

, In: 2020 IEEE Symposium on VLSI Technology,
Gupta, A. ; Mertens, H. ; Tao, Z.... - p. 1-2 , 2020
 
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15

Ge oxide scavenging and gate stack nitridation for strained..:

, In: 2019 IEEE International Electron Devices Meeting (IEDM),
Arimura, H. ; Wostyn, K. ; Ragnarsson, L.-A.... - p. 29.2.1-29.2.4 , 2019
 
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