Hanho Lee
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1

A high-speed four-parallel radix-24 FFT/IFFT processor for ..:

, In: 2008 IEEE International Symposium on Circuits and Systems (ISCAS),
Minhyeok Shin ; Hanho Lee - p. None , 2008
 
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2

Adaptive quantization in min-sum based irregular LDPC decod..:

, In: 2008 IEEE International Symposium on Circuits and Systems (ISCAS),
 
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3

Two bit-level pipelined viterbi decoder for high-performanc..:

, In: 2008 IEEE International Symposium on Circuits and Systems (ISCAS),
Yong-Je Goo ; Hanho Lee - p. None , 2008
 
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4

High-speed VLSI architecture for parallel Reed-Solomon deco..:

Hanho Lee
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  11 (2003)  2 - p. 288-294 , 2003
 
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7

Hardware Circuits and Systems Design for Post-Quantum Crypt..:

Xie, Jiafeng ; Zhao, Wenfeng ; Lee, Hanho..
IEEE Transactions on Circuits and Systems II: Express Briefs.  71 (2024)  3 - p. 1670-1676 , 2024
 
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8

Compact 217 NTT Architecture for Fully Homomorphic Encrypti..:

, In: 2024 IEEE International Symposium on Circuits and Systems (ISCAS),
Mareta, Rella ; Lee, Hanho - p. 1-5 , 2024
 
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11

Twiddle Factor Generator Architecture for Number Theoretic ..:

, In: 2023 20th International SoC Design Conference (ISOCC),
Lee, Chulwoo ; Lee, Hanyoung ; Duong-Ngoc, Phap. - p. 209-210 , 2023
 
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12

Hamming-Distance Trellis Min-Max-Based Architecture for Non..:

Xuan Pham, Thang ; Tan Nguyen, Tuy ; Lee, Hanho
IEEE Transactions on Circuits and Systems II: Express Briefs.  70 (2023)  7 - p. 2390-2394 , 2023
 
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14

An Efficient Unified Polynomial Arithmetic Unit for CRYSTAL..:

Pham, Thang Xuan ; Duong-Ngoc, Phap ; Lee, Hanho
IEEE Transactions on Circuits and Systems I: Regular Papers.  70 (2023)  12 - p. 4854-4864 , 2023
 
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