Hikavyy, A.
113  results:
Search for persons X
?
1

Nanosheet-based Device Architectures with Front/Backside Co..:

, In: 2023 21st International Workshop on Junction Technology (IWJT),
Veloso, A. ; Eneman, G. ; Matagne, P.... - p. 1-5 , 2023
 
?
2

Comprehensive 300 mm process for Silicon spin qubits with m..:

, In: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits),
 
?
3

Nanosheet-based Complementary Field-Effect Transistors (CFE..:

, In: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits),
Mertens, H. ; Hosseini, M. ; Chiarella, T.... - p. 1-2 , 2023
 
?
4

Low temperature source/drain epitaxy and functional silicid..:

, In: 2022 International Electron Devices Meeting (IEDM),
Porret, C. ; Everaert, J.-L. ; Schaekers, M.... - p. 34.1.1-34.1.4 , 2022
 
?
5

Innovations in Transistor Architecture and Device Connectiv..:

, In: 2022 International Conference on IC Design and Technology (ICICDT),
Veloso, A. ; Eneman, G. ; De Keersgieter, A.... - p. 51-54 , 2022
 
?
6

Forksheet FETs with Bottom Dielectric Isolation, Self-Align..:

, In: 2022 International Electron Devices Meeting (IEDM),
Mertens, H. ; Ritzenthaler, R. ; Oniki, Y.... - p. 23.1.1-23.1.4 , 2022
 
?
7

Demonstration of 3D sequential FD-SOI on CMOS FinFET stacki..:

, In: 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits),
Vandooren, A. ; Parihar, N. ; Franco, J.... - p. 330-331 , 2022
 
?
8

Scaled FinFETs Connected by Using Both Wafer Sides for Rout..:

, In: 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits),
Veloso, A. ; Jourdain, A. ; Radisic, D.... - p. 284-285 , 2022
 
?
9

Epitaxial Growth of Active Si on Top of SiGe Etch Stop Laye..:

Loo, R. ; Jourdain, A. ; Rengo, G....
ECS Journal of Solid State Science and Technology.  10 (2021)  1 - p. 014001 , 2021
 
?
10

Comparison of Electrical Performance of Co-Integrated Forks..:

, In: 2021 IEEE International Electron Devices Meeting (IEDM),
Ritzenthaler, R. ; Mertens, H. ; Eneman, G.... - p. 26.2.1-26.2.4 , 2021
 
?
11

3D sequential low temperature top tier devices using dopant..:

, In: 2020 IEEE Symposium on VLSI Technology,
Vandooren, A. ; Wu, Z. ; Parihar, N.... - p. 1-2 , 2020
 
?
 
?
13

Vertical Nanowire and Nanosheet FETs: Device Features, Nove..:

, In: 2019 IEEE International Electron Devices Meeting (IEDM),
Veloso, A. ; Hikavyy, A. ; Loo, R.... - p. 11.1.1-11.1.4 , 2019
 
?
14

TEM investigations of gate-all-around nanowire devices:

Favia, P ; Richard, O ; Eneman, G...
Semiconductor Science and Technology.  34 (2019)  12 - p. 124003 , 2019
 
?
15

Dangling bond defects in silicon-passivated strained-Si1−xG..:

Madia, O. ; Kepa, J. ; Afanas'ev, V. V....
Journal of Materials Science: Materials in Electronics.  31 (2019)  1 - p. 75-79 , 2019
 
1-15