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Hong, Xianlong
340  results:
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1

Rethinking thermal via planning with timing-power-temperatu..:

, In: Proceedings of the 16th Asia and South Pacific Design Automation Conference,
Wang, Kan ; Ma, Yuchun ; Dong, Sheqin... - p. 261-266 , 2011
Link: https://dl.acm.org/doi/1..
 
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2

Leakage-Aware TSV-Planning with Power-Temperature-Delay Dep..:

WANG, Kan ; DONG, Sheqin ; MA, Yuchun...
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences.  E94-A (2011)  12 - p. 2490-2498 , 2011
Link: https://doi.org/10.1587/..
 
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3

ECP- and CMP-Aware Detailed Routing Algorithm for DFM:

Shen, Yin ; Zhou, Qiang ; Cai, Yici.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  18 (2010)  1 - p. 153-157 , 2010
Link: https://doi.org/10.1109/..
 
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4

An Effective Gated Clock Tree Design Based on Activity and ..:

Shen, Weixiang ; Cai, Yici ; Hong, Xianlong.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  18 (2010)  12 - p. 1639-1648 , 2010
Link: https://doi.org/10.1109/..
 
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5

Effective congestion reduction for IC package substrate rou..:

Liu, Shenghua ; Chen, Guoqiang ; Jing, Tom Tong...
ACM Transactions on Design Automation of Electronic Systems (TODAES).  15 (2010)  3 - p. 1-21 , 2010
Link: https://dl.acm.org/doi/1..
 
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6

PS-FPG : pattern selection based co-design of floorplan ..:

, In: Proceedings of the 2010 Asia and South Pacific Design Automation Conference,
Li, Li ; Ma, Yuchun ; Xu, Ning.. - p. 769-774 , 2010
Link: https://dl.acm.org/doi/1..
 
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7

Efficient Power Network Analysis with Modeling of Inductive..:

ZENG, Shan ; YU, Wenjian ; HONG, Xianlong.
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences.  E93-A (2010)  6 - p. 1196-1203 , 2010
Link: https://doi.org/10.1587/..
 
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8

Effective congestion reduction for IC package substrate rou..:

Liu, Shenghua ; Chen, Guoqiang ; Jing, Tom Tong...
ACM Transactions on Design Automation of Electronic Systems.  15 (2010)  3 - p. 1-21 , 2010
Link: https://doi.org/10.1145/..
 
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9

Simultaneous slack budgeting and retiming for synchronous c..:

, In: Proceedings of the 2010 Asia and South Pacific Design Automation Conference,
Liu, Shenghua ; Ma, Yuchun ; Hong, Xianlong. - p. 49-54 , 2010
Link: https://dl.acm.org/doi/1..
 
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10

Thermal aware placement in 3D ICs using quadratic uniformit..:

Yan, Haixia ; Zhou, Qiang ; Hong, Xianlong
Integration.  42 (2009)  2 - p. 175-180 , 2009
Link: https://doi.org/10.1016/..
 
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11

Integrated interlayer via planning and pin assignment for 3..:

, In: Proceedings of the 11th international workshop on System level interconnect prediction,
He, Xu ; Dong, Sheqin ; Hong, Xianlong. - p. 99-104 , 2009
Link: https://dl.acm.org/doi/1..
 
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12

A single layer zero skew clock routing in X architecture:

Shen, WeiXiang ; Cai, YiCi ; Hong, XianLong..
Science in China Series F: Information Sciences.  52 (2009)  8 - p. 1466-1475 , 2009
Link: https://doi.org/10.1007/..
 
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13

Efficient Partial Reluctance Extraction for Large-Scale Reg..:

ZENG, Shan ; YU, Wenjian ; SHI, Jin..
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences.  E92-A (2009)  6 - p. 1476-1484 , 2009
Link: https://doi.org/10.1587/..
 
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14

A novel thermal optimization flow using incremental floorpl..:

, In: Proceedings of the 2009 Asia and South Pacific Design Automation Conference,
Li, Xin ; Ma, Yuchun ; Hong, Xianlong - p. 347-352 , 2009
Link: https://dl.acm.org/doi/1..
 
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15

An efficient decoupling capacitance optimization using piec..:

, In: Proceedings of the Conference on Design, Automation and Test in Europe,
Wang, Xiaoyi ; Cai, Yici ; Tan, Sheldon X.-D... - p. 1190-1195 , 2009
Link: https://dl.acm.org/doi/1..
 
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