Hosokawa, Toshinori
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1

CRLock: A SAT and FALL Attacks Resistant Logic Locking Meth..:

YOSHIMURA, Masayoshi ; TSUJIKAWA, Atsuya ; HOSOKAWA, Toshinori
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences.  E107.A (2024)  3 - p. 583-591 , 2024
 
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2

A Block Partitioning Method for Region Exhaustive Test to R..:

, In: 2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT),
 
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3

An Evaluation of a Testability Measure for State Assignment..:

, In: 2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT),
 
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4

An Evaluation of Estimated Field Random Testability for Dat..:

, In: 2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT),
 
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5

An Estimation Method of Defect Types Using Artificial Neura..:

, In: 2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT),
 
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6

CRLock: A SAT and FALL Attacks Resistant Logic Locking Meth..:

, In: 2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT),
 
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7

Universal Testing for Linear Feed-Forward/Feedback Shift Re..:

FUJIWARA, Hideo ; FUJIWARA, Katsuya ; HOSOKAWA, Toshinori
IEICE Transactions on Information and Systems.  E103.D (2020)  5 - p. 1023-1030 , 2020
 
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8

A Test Sensitization State Compaction Method on Controller ..:

, In: 2020 IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS),
 
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9

A Multiple Target Test Generation Method for Gate-Exhaustiv..:

, In: 2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT),
 
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10

A Low Capture Power Oriented X-Identification-Filling Co-Op..:

, In: 2020 IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS),
 
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11

A State Assignment Method to Improve Transition Fault Cover..:

, In: 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT),
 
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12

A Low Capture Power Oriented X-filling Method Using Partial..:

, In: 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT),
 
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13

A Low Capture Power Test Generation Method Based on Capture..:

HOSOKAWA, Toshinori ; HIRAI, Atsushi ; YAMAUCHI, Yukari.
IEICE Transactions on Information and Systems.  E100.D (2017)  9 - p. 2118-2125 , 2017
 
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14

A Don't Care Filling Method for Low Capture Power based on ..:

YOSHIMURA, Masayoshi ; TAKAHASHI, Yoshiyasu ; YAMAZAKI, Hiroshi.
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences.  E100.A (2017)  12 - p. 2824-2833 , 2017
 
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15

A Test Compaction Oriented Don't Care Identification Method..:

YAMAZAKI, Hiroshi ; WAKAZONO, Motohiro ; HOSOKAWA, Toshinori.
IEICE Transactions on Information and Systems.  E96.D (2013)  9 - p. 1994-2002 , 2013
 
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