Jeon, Sanghun
308  results:
Search for persons X
?
1

Effect of Annealing Temperature on Minimum Domain Size of F..:

Yun, Seokjung ; Kim, Hoon ; Seo, Myungsoo...
ACS Applied Electronic Materials.  6 (2024)  4 - p. 2134-2141 , 2024
 
?
5

Monolithically Integrated Complementary Ferroelectric FET X..:

Hwang, Junghyeon ; Joh, Hongrae ; Kim, Chaeheon..
ACS Applied Materials & Interfaces.  16 (2024)  2 - p. 2467-2476 , 2024
 
?
6

Charge Trap Flash with Superior Program Efficiency by Negat..:

, In: 2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA),
Kim, Giuk ; Choi, Hyojun ; Lee, Sangho... - p. 1-2 , 2024
 
?
7

Ultrafast (50 ns) ID–VG Analysis on Oxide Thin-Film Transis..:

Jung, Taeseung ; Nam, Sooji ; Jeon, Sanghun
IEEE Transactions on Electron Devices.  71 (2024)  5 - p. 3009-3014 , 2024
 
?
9

Novel Strategies Toward High-Performance FeFET for Computin..:

, In: 2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA),
Kim, Giuk ; Choi, Hyojun ; Lee, Sangho... - p. 1-2 , 2024
 
?
10

Design Guidelines of Hafnia Ferroelectrics and Gate-Stack f..:

Lee, Sangho ; Kim, Giuk ; Lee, Youngkyu...
IEEE Transactions on Electron Devices.  71 (2024)  3 - p. 1865-1871 , 2024
 
?
13

Comprehensive Design Guidelines of Gate Stack for QLC and H..:

, In: 2023 International Electron Devices Meeting (IEDM),
Lim, Suhwan ; Kim, Taeyoung ; Myeong, Ilho... - p. 1-4 , 2023
 
?
14

Ultra-high Tunneling Electroresistance Ratio (2 × 104) & En..:

, In: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits),
 
?
 
1-15