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Jin, Jahoon
18  results:
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1

A 4-nm 16-Gb/s/pin Single-Ended PAM-4 Parallel Transceiver ..:

Jin, Jahoon ; Lee, Soo-Min ; Min, Kyunghwan...
IEEE Journal of Solid-State Circuits.  59 (2024)  1 - p. 184-195 , 2024
Link: https://doi.org/10.1109/..
 
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2

The design of non‐stacked and symmetric XOR for high‐speed ..:

Park, Minsu ; Jin, Jahoon ; Park, Sehoon.
Electronics Letters.  59 (2023)  13 - p. , 2023
Link: https://doi.org/10.1049/..
 
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3

A 4nm 16Gb/s/pin Single-Ended PAM4 Parallel Transceiver wit..:

, In: 2023 IEEE International Solid- State Circuits Conference (ISSCC),
Jin, Jahoon ; Lee, Soo-Min ; Min, Kyunghwan... - p. 1-3 , 2023
Link: https://doi.org/10.1109/..
 
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4

A 5.0-to-12.5-Gb/s, 1.7-pJ/b, 0.66-μs Lock-time Reference-l..:

, In: 2022 IEEE Asian Solid-State Circuits Conference (A-SSCC),
Park, Woosung ; Jin, Jahoon ; Park, Minsu.. - p. 1-3 , 2022
Link: https://doi.org/10.1109/..
 
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5

A 16/32 Gb/s Dual-Mode NRZ/PAM4 Voltage-Mode Transmitter Wi..:

Kim, Sung-Ha ; Cho, Byungwook ; Jin, Jahoon..
IEEE Access.  10 (2022)  - p. 119140-119149 , 2022
Link: https://doi.org/10.1109/..
 
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6

A 3nm GAAFET Analog Assisted Digital LDO with High Current ..:

, In: 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits),
Kim, Seki ; Lee, Hyongmin ; Lee, Yongjin... - p. 190-191 , 2022
Link: https://doi.org/10.1109/..
 
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7

A Referenceless Digital CDR with a Half-Rate Jitter-Toleran..:

Kim, Jaekwon ; Ko, Youngjun ; Jin, Jahoon..
Electronics.  11 (2022)  4 - p. 537 , 2022
Link: https://doi.org/10.3390/..
 
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8

A Jitter-Tolerant Referenceless Digital-CDR for Cellular Tr..:

, In: 2020 IEEE Asian Solid-State Circuits Conference (A-SSCC),
Kim, Jaekwon ; Ko, Youngjun ; Jin, Jahoon.. - p. 1-4 , 2020
Link: https://doi.org/10.1109/..
 
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9

A 4.0-10.0-Gb/s Referenceless CDR with Wide-Range, Jitter-T..:

, In: ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC),
Jin, Jahoon ; Kim, Jaekwon ; Kim, Hyeran... - p. 146-149 , 2018
Link: https://doi.org/10.1109/..
 
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10

A 12.5-Gb/s Near-Ground Transceiver Employing a MaxEye Algo..:

Jin, Jahoon ; Kim, Seok ; Jin, Xuefan..
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  26 (2018)  3 - p. 522-530 , 2018
Link: https://doi.org/10.1109/..
 
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11

The design of non‐stacked and symmetric XOR for high‐speed ..:

Minsu Park ; Jahoon Jin ; Sehoon Park.
https://doi.org/10.1049/ell2.12850.  , 2023
Link: https://doi.org/10.1049/..
 
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12

A Referenceless Digital CDR with a Half-Rate Jitter-Toleran..:

Jaekwon Kim ; Youngjun Ko ; Jahoon Jin..
https://www.mdpi.com/2079-9292/11/4/537.  , 2022
Link: https://doi.org/10.3390/..
 
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13

A 16/32 Gb/s Dual-Mode NRZ/PAM4 Voltage-Mode Transmitter Wi..:

Sung-Ha Kim ; Byungwook Cho ; Jahoon Jin..
https://ieeexplore.ieee.org/document/9942817/.  , 2022
Link: https://doi.org/10.1109/..
 
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14

A Referenceless Digital CDR with a Half-Rate Jitter-Toleran..:

Jaekwon Kim ; Youngjun Ko ; Jahoon Jin..
Circuit and Signal Processing.  , 2022
Link: https://doi.org/10.3390/..
 
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15

Double wavy geometric disturbance to the bluff body flow at..:

Yoon, Hyun Sik ; Oh, Kyung Jin ; Kim, Hyo Ju..
Ocean Engineering.  195 (2020)  - p. 106713 , 2020
Link: https://doi.org/10.1016/..
 
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