Kim, Sangjin
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1

Two-Step Spike Encoding Scheme and Architecture for Highly ..:

, In: 2024 IEEE International Symposium on Circuits and Systems (ISCAS),
Kim, Sangyeob ; Kim, Sangjin ; Um, Soyeon.. - p. 1-5 , 2024
 
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3

DynaPlasia: An eDRAM In-Memory Computing-Based Reconfigurab..:

Kim, Sangjin ; Li, Zhiyong ; Um, Soyeon...
IEEE Journal of Solid-State Circuits.  59 (2024)  1 - p. 102-115 , 2024
 
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4

An Overview of Computing-in-Memory Circuits With DRAM and N..:

Kim, Sangjin ; Yoo, Hoi-Jun
IEEE Transactions on Circuits and Systems II: Express Briefs.  71 (2024)  3 - p. 1626-1631 , 2024
 
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7

20.5 C-Transformer: A 2.6-18.1μJ/Token Homogeneous DNN-Tran..:

, In: 2024 IEEE International Solid-State Circuits Conference (ISSCC),
Kim, Sangyeob ; Kim, Sangjin ; Jo, Wooyoung... - p. 368-370 , 2024
 
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8

C-DNN: An Energy-Efficient Complementary Deep-Neural-Networ..:

Kim, Sangyeob ; Kim, Soyeon ; Hong, Seongyon...
IEEE Journal of Solid-State Circuits.  59 (2024)  1 - p. 157-172 , 2024
 
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12

NoPIM: Functional Network-on-Chip Architecture for Scalable..:

, In: 2024 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS),
Kim, Sangjin ; Li, Zhiyong ; Um, Soyeon... - p. 1-3 , 2024
 
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15

Two-Stage Classification Method for Individual Workout Stat..:

Noh, Yoonjae ; Yoon, YoonIl ; Kim, Sangjin
Measurement: Interdisciplinary Research and Perspectives.  22 (2024)  1 - p. 121-129 , 2024
 
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