E-LIB Suche - Ergebnisse für: Kumar, Ramayya

1

JESSI AC-8 "Synthesis, optimization and analysis"

BMBF-Abschlußbericht ; [final technical report, main phase ...

Herrmann, Ronald ; Kumar, Ramayya - [Electronic ed.] . , 1998

Link: http://edok01.tib.uni-ha..

2

JESSI applications project AC-8: Synthesis, optimization an..

final technical report, main phase II, rev. 1.0 ; reporting...

Riedel, Steffen ; Brand, Hans-Jürgen ; Kumar, Ramayya - [Electronic ed.] . , 1997

Link: http://edok01.tib.uni-ha..

3

Theorem provers in circuit design

theory, practice and experience ; proceedings Lecture notes in computer science ; 901

Kumar, Ramayya , 1995

Copies: Zentrale:Magazin 01.P.5693

4

Theorem provers in circuit design

theory, practice and experience ; second international conf... Lecture notes in computer science ; 901

Kumar, Ramayya , 1995

Link: http://dx.doi.org/10.100..

Copies: Zentrale:Magazin 01.P.5693

5

Theorem Provers in Circuit Design

Theory, Practice and Experience Lecture Notes in Computer Science ; 901;SpringerLink, Bücher

Kumar, Ramayya ; Kropf, Thomas , 1995

Link: https://doi.org/10.1007/..

6

Formal verification of pipeline conflicts in RISC processor:

, In: Proceedings of the conference on European design automation,

Kumar, Ramayya ; Tahar, Sofiène - p. 284-289 , 1994

Link: https://dl.acm.org/doi/1..

7

Accelerating tableaux proofs using compact representations:

Schneider, Klaus ; Kumar, Ramayya ; Kropf, Thomas
Formal Methods in System Design. 5 (1994) 1-2 - p. 145-176 , 1994

Link: https://doi.org/10.1007/..

8

Structuring and automating hardware proofs in a higher-orde..:

Kumar, Ramayya ; Schneider, Klaus ; Kropf, Thomas
Formal Methods in System Design. 2 (1993) 2 - p. 165-223 , 1993

Link: https://doi.org/10.1007/..

9

A Formalization of a Hierarchical Model for RISC Processors:

, In: Informatik aktuell; Europäischer Informatik Kongreß Architektur von Rechensystemen Euro-ARCH '93,

Tahar, Sofiène ; Kumar, Ramayya - p. 591-602 , 1993

Link: https://doi.org/10.1007/..

10

Verification of synthesized circuits at register transfer l..:

, In: Proceedings of the conference on European design automation,

Feldbusch, Fridtjof ; Kumar, Ramayya - p. 22-26 , 1991

Link: https://dl.acm.org/doi/1..

11

An automated data path synthesizer for a canonic structure,..:

, In: Proceedings of the 22nd ACM/IEEE Design Automation Conference,

Ramayya, Kumar ; Kumar, Anshul ; Prasad, Surendra - p. 381-387 , 1985

Link: https://dl.acm.org/doi/1..

12

A formal model for a VHDL subset of synchronous circuits:

Eisenbiegler, Dirk ; Kumar, Ramayya ; Mueller, J
https://publikationen.bibliothek.kit.edu/339196. , 2007

Link: https://publikationen.bi..

13

Applicability of formal synthesis illustrated via schedulin:

Blumenroehr, Christian ; Eisenbiegler, Dirk ; Kumar, Ramayya
https://publikationen.bibliothek.kit.edu/339596. , 2007

Link: https://publikationen.bi..

14

A constructive approach towards correctness of synthesis - ..:

Eisenbiegler, Dirk ; Kumar, Ramayya ; Blumenroehr, Christian
info:eu-repo/semantics/altIdentifier/isbn/0-8186-7786-4. , 1997

Link: https://publikationen.bi..

15

Implementation issues about the embedding of existing high ..:

Eisenbiegler, Dirk ; Blumenroehr, Christian ; Kumar, Ramayya
Lecture notes in computer science. , 1996

Link: https://publikationen.bi..