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Lacaita, Andrea
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1

A 2-GS/s Time-Interleaved ADC With Embedded Background Cali..:

Ricci, Luca ; Bè, Gabriele ; Rocco, Michele...
IEEE Journal of Solid-State Circuits.  , 2024
Link: https://doi.org/10.1109/..
 
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2

A 66.7fs-Integrated-Jitter Fractional-N Digital PLL Based o..:

, In: 2024 IEEE Custom Integrated Circuits Conference (CICC),
Salvi, Pietro ; Dartizio, Simone M. ; Rossoni, Michele... - p. 1-2 , 2024
Link: https://doi.org/10.1109/..
 
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3

A 59.3fs Jitter and -62.1dBc Fractional-Spur Digital PLL Ba..:

, In: 2024 IEEE Custom Integrated Circuits Conference (CICC),
Dartizio, Simone M. ; Rossoni, Michele ; Tesolin, Francesco... - p. 1-2 , 2024
Link: https://doi.org/10.1109/..
 
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4

4.3 A 76.7fs-lntegrated-Jitter and −71.9dBc In-Band Fractio..:

, In: 2023 IEEE International Solid- State Circuits Conference (ISSCC),
Dartizio, Simone M. ; Tesolin, Francesco ; Castoro, Giacomo... - p. 3-5 , 2023
Link: https://doi.org/10.1109/..
 
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5

Phase Noise Analysis of Periodically ON/OFF Switched Oscill..:

Castoro, Giacomo ; Dartizio, Simone M. ; Lacaita, Andrea L..
IEEE Transactions on Circuits and Systems I: Regular Papers.  70 (2023)  1 - p. 54-63 , 2023
Link: https://doi.org/10.1109/..
 
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6

A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on..:

Dartizio, Simone M. ; Tesolin, Francesco ; Castoro, Giacomo...
IEEE Journal of Solid-State Circuits.  58 (2023)  12 - p. 3320-3337 , 2023
Link: https://doi.org/10.1109/..
 
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7

A Novel LO Phase-Shifting System Based on Digital Bang-Bang..:

Tesolin, Francesco ; Dartizio, Simone M. ; Buccoleri, Francesco...
IEEE Journal of Solid-State Circuits.  58 (2023)  9 - p. 2466-2477 , 2023
Link: https://doi.org/10.1109/..
 
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8

4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation..:

, In: 2023 IEEE International Solid- State Circuits Conference (ISSCC),
Castoro, Giacomo ; Dartizio, Simone M. ; Tesolin, Francesco... - p. 82-84 , 2023
Link: https://doi.org/10.1109/..
 
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9

A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digit..:

Buccoleri, Francesco ; Dartizio, Simone M. ; Tesolin, Francesco...
IEEE Journal of Solid-State Circuits.  58 (2023)  3 - p. 634-646 , 2023
Link: https://doi.org/10.1109/..
 
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10

A 2GS/s 11b 8x Interleaved ADC with 9.2 ENOB and 69.9dB SFD..:

, In: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits),
Ricci, Luca ; Scaletti, Lorenzo ; Be, Gabriele... - p. 1-2 , 2023
Link: https://doi.org/10.23919..
 
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11

A 900-MS/s SAR-Based Time-Interleaved ADC With a Fully Prog..:

Be, Gabriele ; Parisi, Angelo ; Bertulessi, Luca...
IEEE Transactions on Circuits and Systems II: Express Briefs.  69 (2022)  9 - p. 3645-3649 , 2022
Link: https://doi.org/10.1109/..
 
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12

A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase D..:

Dartizio, Simone M. ; Tesolin, Francesco ; Mercandelli, Mario...
IEEE Journal of Solid-State Circuits.  57 (2022)  6 - p. 1723-1735 , 2022
Link: https://doi.org/10.1109/..
 
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13

Analysis and Design of 8-to-101.6-GHz Injection-Locked Freq..:

Garghetti, Alessandro ; Lacaita, Andrea L. ; Seebacher, David..
IEEE Journal of Solid-State Circuits.  57 (2022)  6 - p. 1788-1799 , 2022
Link: https://doi.org/10.1109/..
 
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14

A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs..:

Mercandelli, Mario ; Santiccioli, Alessio ; Parisi, Angelo...
IEEE Journal of Solid-State Circuits.  57 (2022)  2 - p. 505-517 , 2022
Link: https://doi.org/10.1109/..
 
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15

A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PL..:

, In: 2022 IEEE Custom Integrated Circuits Conference (CICC),
Buccoleri, Francesco ; Dartizio, Simone M. ; Tesolin, Francesco... - p. 1-2 , 2022
Link: https://doi.org/10.1109/..
 
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