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Lahgere, Avinash
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1

Scalability Prespective of Nanotube TFET Capacitorless DRAM..:

, In: 2024 IEEE Latin American Electron Devices Conference (LAEDC),
Kamal, Alok Kumar ; Kamal, Neha ; Lahgere, Avinash - p. 1-4 , 2024
Link: https://doi.org/10.1109/..
 
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2

Design of Leaky Integrate and Fire Neuron for Spiking Neura..:

Lahgere, Avinash
IEEE Transactions on Nanotechnology.  22 (2023)  - p. 260-265 , 2023
Link: https://doi.org/10.1109/..
 
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3

Gate Grounded Trench I-MOS as an ESD Clamp for Sub-2V Appli..:

Lahgere, Avinash ; Gupta, Dhruv Shikhar
IEEE Access.  11 (2023)  - p. 108938-108943 , 2023
Link: https://doi.org/10.1109/..
 
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4

Ultra-Low Power Reconfigurable Synaptic and Neuronal Transi..:

Kamal, Neha ; Singh, Jawar ; Lahgere, Avinash.
IEEE Transactions on Nanotechnology.  22 (2023)  - p. 245-251 , 2023
Link: https://doi.org/10.1109/..
 
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5

A Simulation Study of Bipolar I-MOS for ESD Protection:

Lahgere, Avinash ; Gupta, Dhruv Shikhar
IEEE Transactions on Electron Devices.  70 (2023)  12 - p. 6687-6690 , 2023
Link: https://doi.org/10.1109/..
 
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6

Dopingless ferroelectric tunnel FET architecture for the im..:

Lahgere, Avinash ; Panchore, Meena ; Singh, Jawar
Superlattices and Microstructures.  96 (2016)  - p. 16-25 , 2016
Link: https://doi.org/10.1016/..
 
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7

A Dynamically Configurable Silicon Nanowire Field Effect Tr..:

Sahu, Chitrakant ; Lahgere, Avinash ; Singh, Jawar
http://arxiv.org/abs/1412.4975.  , 2014
Link: http://arxiv.org/abs/141..
 
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8

Gate Grounded Trench I-MOS as an ESD Clamp for Sub-2V Appli..:

Avinash Lahgere ; Dhruv Shikhar Gupta
https://ieeexplore.ieee.org/document/10271368/.  , 2023
Link: https://doi.org/10.1109/..
 
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