Lin, Rung-Bin
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1

Routing Intent Aware Pin Access Point Selection for Standar..:

, In: 2024 25th International Symposium on Quality Electronic Design (ISQED),
 
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2

Sub-10nm Standard Cell Library Design Methodology for On-Gr..:

, In: 2024 IEEE International Symposium on Circuits and Systems (ISCAS),
Lin, Rung-Bin ; Lu, Pei-Sheng - p. 1-5 , 2024
 
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3

Improving Pin Accessibility of Standard Cells under Power/G..:

, In: 2023 21st IEEE Interregional NEWCAS Conference (NEWCAS),
Lu, Pei-Sheng ; Lin, Rung-Bin - p. 1-5 , 2023
 
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4

Improving Pin Accessibility of Standard Cell Libraries in 7..:

, In: 2022 23rd International Symposium on Quality Electronic Design (ISQED),
 
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5

Engineering a Standard Cell Library for an Industrial Route..:

, In: 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI),
Chung, Yuan-Dar ; Lin, Rung-Bin - p. 404-409 , 2020
 
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6

A Maze Routing-Based Methodology With Bounded Exploration a..:

Lin, Kuen-Wey ; Lin, Yeh-Sheng ; Li, Yih-Lang.
ACM Transactions on Design Automation of Electronic Systems (TODAES).  23 (2018)  4 - p. 1-26 , 2018
 
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7

A Maze Routing-Based Methodology With Bounded Exploration a..:

Lin, Kuen-Wey ; Lin, Yeh-Sheng ; Li, Yih-Lang.
ACM Transactions on Design Automation of Electronic Systems.  23 (2018)  4 - p. 1-26 , 2018
 
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8

Overview of the 2017 CAD contest at ICCAD:

, In: Proceedings of the 36th International Conference on Computer-Aided Design,
Kim, Myung-Chul ; Huang, Shih-Hsu ; Lin, Rung-Bin. - p. 855-856 , 2017
 
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9

A Maze Routing-Based Algorithm for ML-OARST with Pre-Select..:

, In: Proceedings of the Great Lakes Symposium on VLSI 2017,
Lin, Kuen-Wey ; Lin, Yeh-Sheng ; Li, Yih-Lang. - p. 399-402 , 2017
 
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10

Overview of the 2016 CAD contest at ICCAD:

, In: Proceedings of the 35th International Conference on Computer-Aided Design,
 
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11

Overview of the 2015 CAD Contest at ICCAD:

, In: Proceedings of the IEEE/ACM International Conference on Computer-Aided Design,
 
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12

Simultaneous transistor pairing and placement for CMOS stan..:

, In: Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition,
Lu, Ang ; Lu, Hsueh-Ju ; Jang, En-Jang... - p. 1647-1652 , 2015
 
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13

Logic block and design methodology for via-configurable str..:

, In: Proceedings of the 24th edition of the great lakes symposium on VLSI,
Lin, Ta-Kai ; Lin, Kuen-Wey ; Chiu, Chang-Hao. - p. 111-116 , 2014
 
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14

Session details: Poster session 1:

, In: Proceedings of the 24th edition of the great lakes symposium on VLSI,
Lin, Rung-Bin , 2014
 
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15

Slack budgeting and slack to length converting for multi-bi..:

, In: Proceedings of the Conference on Design, Automation and Test in Europe,
Lu, Chia-Chieh ; Lin, Rung-Bin - p. 1837-1842 , 2013
 
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