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Liu, Shen-Iuan
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1

A 48-Gb/s Baud-Rate PAM-4 Receiver With One-Tap Speculative..:

, In: 2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA),
Huang, Yuan-Pang ; Liu, Shen-Iuan - p. 1-4 , 2024
Link: https://doi.org/10.1109/..
 
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2

A 16-Gb/s Baud-Rate CDR Circuit With One-Tap Speculative DF..:

Chou, Po-Yuan ; Chen, Wei-Ming ; Liu, Shen-Iuan
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  32 (2024)  3 - p. 480-484 , 2024
Link: https://doi.org/10.1109/..
 
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3

A 36-Gb/s 2× Half-Baud-Rate Adaptive Receiver in 28-nm CMOS:

Lan, Yi-Hao ; Liu, Shen-Iuan
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  32 (2024)  7 - p. 1263-1272 , 2024
Link: https://doi.org/10.1109/..
 
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4

A 20-Gb/s Jitter-Tolerance-Enhanced Baud-Rate CDR Circuitwi..:

, In: 2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA),
Peng, Hsi-Kai ; Liu, Shen-Iuan - p. 1-4 , 2024
Link: https://doi.org/10.1109/..
 
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5

A 12.93–16 Gb/s Reference-Less Baud-Rate CDR Circuit With O..:

Peng, Hsi-Kai ; Liu, Shen-Iuan
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  32 (2024)  4 - p. 787-791 , 2024
Link: https://doi.org/10.1109/..
 
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6

A 0.079-pJ/b/dB 32-Gb/s 2× Half-Baud-Rate CDR Circuit With ..:

Lan, Yi-Hao ; Liu, Shen-Iuan
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  32 (2024)  4 - p. 704-713 , 2024
Link: https://doi.org/10.1109/..
 
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7

A 48-Gb/s Baud-Rate PAM-4 Receiver Using Modified Time-Inte..:

Huang, Yuan-Pang ; Liu, Shen-Iuan
IEEE Transactions on Circuits and Systems II: Express Briefs.  , 2024
Link: https://doi.org/10.1109/..
 
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8

A 40-Gb/s PAM-3 Receiver With Modified Summer-Merged Slicer..:

Lin, Jhe-En ; Lan, Yi-Hao ; Liu, Shen-Iuan
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  , 2024
Link: https://doi.org/10.1109/..
 
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9

A 14.7-20-Gb/s Reference-Less Baud-Rate CDR Circuit with On..:

, In: 2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA),
Chou, Po-Yuan ; Liu, Shen-Iuan - p. 1-4 , 2024
Link: https://doi.org/10.1109/..
 
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10

A 0.0072-mm2 10-bit 100-MS/s Calibration-free SAR ADC Using..:

, In: 2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT),
Tsai, Yao-Hung ; Liu, Shen-Iuan - p. 1-4 , 2023
Link: https://doi.org/10.1109/..
 
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11

A 1.6-GHz DPLL Using Feedforward Phase-Error Cancellation:

Kang, Zhi-Heng ; Liu, Shen-Iuan
IEEE Journal of Solid-State Circuits.  58 (2023)  3 - p. 806-816 , 2023
Link: https://doi.org/10.1109/..
 
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12

A 7∼10.5-Gb/s Reference-Less Linear Half-rate CDR Circuit U..:

, In: 2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT),
Hsu, Yi-En ; Liu, Shen-Iuan - p. 1-4 , 2023
Link: https://doi.org/10.1109/..
 
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13

A 20-Gb/s Jitter-Tolerance-Enhanced Digital CDR With One-Ta..:

Chen, Wei-Ming ; Yao, Yun-Sheng ; Liu, Shen-Iuan
IEEE Transactions on Circuits and Systems II: Express Briefs.  69 (2022)  3 - p. 894-898 , 2022
Link: https://doi.org/10.1109/..
 
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14

A 2–3 GHz Fast-Locking PLL Using Phase Error Compensator:

Chang, Jia-Rong ; Liu, Shen-Iuan
IEEE Transactions on Circuits and Systems II: Express Briefs.  69 (2022)  4 - p. 2026-2030 , 2022
Link: https://doi.org/10.1109/..
 
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15

An Adaptive Digital PLL Based on BBPFD Transition Probabili..:

, In: 2022 International Symposium on VLSI Design, Automation and Test (VLSI-DAT),
Kang, Zhi-Heng ; Yen, Yu-Chi ; Su, Guan-Yu. - p. 1-4 , 2022
Link: https://doi.org/10.1109/..
 
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