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Marranghello, Felipe
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1

SAT-sweeping enhanced for logic synthesis:

, In: Proceedings of the 57th ACM/EDAC/IEEE Design Automation Conference,
Amarú, Luca ; Marranghello, Felipe ; Testa, Eleonora... - p. 1-6 , 2020
Link: https://dl.acm.org/doi/1..
 
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2

SAT-Sweeping Enhanced for Logic Synthesis:

, In: 2020 57th ACM/IEEE Design Automation Conference (DAC),
Amaru, Luca ; Marranghello, Felipe ; Testa, Eleonora... - p. 1-6 , 2020
Link: https://doi.org/10.1109/..
 
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3

One-Sided Countermeasures for Side-Channel Attacks Can Back..:

, In: Proceedings of the 11th ACM Conference on Security & Privacy in Wireless and Mobile Networks,
Yu, Yang ; Marranghello, Felipe ; Teijeira, Victor Diges. - p. 299-301 , 2018
Link: https://dl.acm.org/doi/1..
 
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4

A Predictive Approach for Conditional Execution of Memristi..:

Dias, Cesar de S. ; Marranghello, Felipe S. ; Brum, Raphael Martins.
IEEE Journal on Emerging and Selected Topics in Circuits and Systems.  12 (2022)  4 - p. 878-887 , 2022
Link: https://doi.org/10.1109/..
 
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5

Improving Analytical Delay Modelingfor CMOS Inverters:

Marranghello, Felipe S. ; Reis, André I. ; Ribas, Renato P.
Journal of Integrated Circuits and Systems.  10 (2020)  2 - p. 123-134 , 2020
Link: https://doi.org/10.29292..
 
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6

Four-Level Forms for Memristive Material Implication Logic:

Marranghello, Felipe S. ; Callegaro, Vinicius ; Reis, Andre I..
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  27 (2019)  5 - p. 1228-1232 , 2019
Link: https://doi.org/10.1109/..
 
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7

SAT-Based Formulation for Logical Capacity Evaluation of VI..:

Bem, Vinicius Dal ; Marranghello, Felipe S. ; Reis, Andre I..
IEEE Transactions on Emerging Topics in Computing.  5 (2017)  2 - p. 247-259 , 2017
Link: https://doi.org/10.1109/..
 
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8

Transistor sizing in lithography-aware regular fabrics:

, In: Proceedings of the 24th symposium on Integrated circuits and systems design,
Marranghello, Felipe dos Santos ; Dal Bem, Vinicius ; Reis, André Inácio.. - p. 97-102 , 2011
Link: https://dl.acm.org/doi/1..
 
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9

Transistor sizing analysis of regular fabrics:

Marranghello, Felipe S ; Dal Bem, Vinicius ; Reis, André I.. , 2011
Link: http://hdl.handle.net/21..
 
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10

Transistor sizing analysis of regular fabrics:

Marranghello, Felipe S ; Dal Bem, Vinicius ; Reis, André Inácio..
Marranghello, F. [et al.]. Transistor sizing analysis of regular fabrics. A: Exploiting Regularity in the Design of IPs, Architectures and Platforms. "1st Workshop on Exploiting Regularity in the Design of IPs, Architectures and Platforms". Como: 2011, p. 235-242..  , 2011
Link: http://hdl.handle.net/21..
 
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11

Logic synthesis for sequential material implication logic b..:

Marranghello, Felipe dos Santos
http://hdl.handle.net/10183/187889.  , 2017
Link: http://hdl.handle.net/10..
 
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12

Implementação de um circuito dedicado para roteamento de da..:

Marranghello, Felipe dos Santos , 2009
Link: http://hdl.handle.net/10..
 
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13

Implementação de um circuito dedicado para roteamento de da..:

Marranghello, Felipe dos Santos , 2009
Link: http://hdl.handle.net/10..
 
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