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Nery, Alexandre S.
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1

Quantum-resistant Cryptography in FPGA:

, In: 2022 Workshop on Communication Networks and Power Systems (WCNPS),
Policarpo, Renata C. ; Nery, Alexandre S. ; Albuquerque, Robson de O. - p. 1-5 , 2022
Link: https://doi.org/10.1109/..
 
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2

A SHA-3 Co-Processor for IoT Applications:

, In: 2020 Workshop on Communication Networks and Power Systems (WCNPS),
Azevedo, Igor L.R. ; Nery, Alexandre S. ; Sena, Alexandre da C. - p. 1-5 , 2020
Link: https://doi.org/10.1109/..
 
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3

Reliability Evaluation of Compressed Deep Learning Models:

, In: 2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS),
Goldstein, Brunno F. ; Srinivasan, Sudarshan ; Das, Dipankar... - p. 1-5 , 2020
Link: https://doi.org/10.1109/..
 
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4

Enabling heterogeneous ray‐tracing acceleration in edge/clo..:

Sampaio, Adrianno A. ; Sena, Alexandre C. ; Nery, Alexandre S.
Concurrency and Computation: Practice and Experience.  33 (2020)  11 - p. , 2020
Link: https://doi.org/10.1002/..
 
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5

A CPU‐FPGA heterogeneous approach for biological sequence c..:

Jorge, Carlos A. C. ; Nery, Alexandre S. ; Melo, Alba C. M. A..
Concurrency and Computation: Practice and Experience.  33 (2020)  4 - p. , 2020
Link: https://doi.org/10.1002/..
 
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6

Design and Evaluation of an SNMP-based Energy Consumption M..:

, In: 2019 Workshop on Communication Networks and Power Systems (WCNPS),
de Almeida, Lucas C. ; de Sousa, Rafael T. ; Nery, Alexandre S.... - p. 1-6 , 2019
Link: https://doi.org/10.1109/..
 
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7

A Re-Configurable Ray-Triangle Vector Accelerator for Emerg..:

, In: 2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW),
Sampaio, Adrianno A. ; Sena, Alexandre C. ; Nery, Alexandre S. - p. 826-833 , 2019
Link: https://doi.org/10.1109/..
 
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8

DF‐DTM: Dynamic Task Memoization and reuse in dataflow:

Rouberte, Leandro ; Sena, Alexandre C. ; Nery, Alexandre S....
Concurrency and Computation: Practice and Experience.  31 (2018)  18 - p. , 2018
Link: https://doi.org/10.1002/..
 
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9

Efficient A* Co-processor for Reconfigurable Gaming Devices:

, In: 2018 17th Brazilian Symposium on Computer Games and Digital Entertainment (SBGames),
Nery, Alexandre S. ; Sena, Alexandre C. - p. 97-9709 , 2018
Link: https://doi.org/10.1109/..
 
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10

Automatic complex instruction identification for efficient ..:

Nery, Alexandre S. ; Nedjah, Nadia ; França, Felipe M. G...
Analog Integrated Circuits and Signal Processing.  85 (2015)  1 - p. 139-158 , 2015
Link: https://doi.org/10.1007/..
 
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11

Hardware reuse in modern application-specific processors an..:

Nery, Alexandre S. ; Jóźwiak, Lech ; Lindwer, Menno...
Microprocessors and Microsystems.  37 (2013)  6-7 - p. 684-692 , 2013
Link: https://doi.org/10.1016/..
 
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12

Efficient hardware implementation of Ray Tracing based on a..:

Nery, Alexandre S. ; Nedjah, Nadia ; França, Felipe M.G.
Journal of Systems Architecture.  59 (2013)  3 - p. 176-185 , 2013
Link: https://doi.org/10.1016/..
 
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13

Parallel processing of intersections for ray-tracing in app..:

Nery, Alexandre S. ; Nedjah, Nadia ; França, Felipe M.G..
Microprocessors and Microsystems.  37 (2013)  6-7 - p. 739-749 , 2013
Link: https://doi.org/10.1016/..
 
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14

An efficient parallel architecture for ray-tracing:

Nery, Alexandre S. ; Nedjah, Nadia ; França, Felipe M. G.
Analog Integrated Circuits and Signal Processing.  70 (2011)  2 - p. 189-202 , 2011
Link: https://doi.org/10.1007/..
 
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15

DTM@GPU: Characterizing and evaluating trace redundancy in ..:

J. Marzulo, Leandro A. ; C. Sena, Alexandre ; S. Nery, Alexandre...
Concurrency and Computation: Practice and Experience.  31 (2018)  18 - p. , 2018
Link: https://doi.org/10.1002/..
 
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