Pal, Ajit
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2

Low-power VLSI circuits and systems:

Pal, Ajit , 2015
Copies:  Zentrale: a elt 697 ef/132
 
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4

Formal Verification of Architectural Power Intent:

Hazra, Aritra ; Goyal, Sahil ; Dasgupta, Pallab.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  21 (2013)  1 - p. 78-91 , 2013
 
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HotSpot minimization using fine-grained DVS architecture at..:

, In: 2012 Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics,
 
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Leveraging UPF-extracted assertions for modeling and formal..:

, In: Proceedings of the 47th Design Automation Conference,
Hazra, Aritra ; Mitra, Srobona ; Dasgupta, Pallab... - p. 773-776 , 2010
 
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Traffic grooming, routing, and wavelength assignment in an ..:

De, Tanmay ; Pal, Ajit ; Sengupta, Indranil
Photonic Network Communications.  20 (2010)  2 - p. 101-112 , 2010
 
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Distributed dynamic grooming routing and wavelength assignm..:

De, Tanmay ; Jain, Puneet ; Pal, Ajit
Photonic Network Communications.  21 (2010)  2 - p. 117-126 , 2010
 
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Low-power microcontroller for wireless sensor networks:

, In: TENCON 2009 - 2009 IEEE Region 10 Conference,
 
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On finding the minimum test set of a BDD-based circuit:

, In: Proceedings of the 16th ACM Great Lakes symposium on VLSI,
 
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Distributed computing - IWDC 2005 

7th international workshop, Kharagpur, India, December 27 -...  Lecture notes in computer science ; 3741
Pal, Ajit , 2005
 
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Distributed Computing ? IWDC 2005 

7th International Workshop, Kharagpur, India, December 27-3...  Lecture Notes in Computer Science ; 3741
 
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15

Synthesis of high performance low power PTL circuits:

, In: Proceedings of the 2003 Asia and South Pacific Design Automation Conference,
Samanta, Debasis ; Dharmadeep, M. C. ; Pal, Ajit - p. 209-212 , 2003
 
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