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Park, Kwanseo
19  results:
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1

A 24.6-29.6GHz Hybrid Sub-Sampling PLL with Tri-State Integ..:

, In: 2024 IEEE International Symposium on Circuits and Systems (ISCAS),
Wang, Zhongkai ; Choi, Minsoo ; Kwon, Paul... - p. 1-5 , 2024
Link: https://doi.org/10.1109/..
 
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2

Analysis of Stochastic Phase-Frequency Detector in 2x Overs..:

Hwang, Young-Ha ; Park, Kwanseo
IEEE Transactions on Circuits and Systems II: Express Briefs.  71 (2024)  4 - p. 1844-1848 , 2024
Link: https://doi.org/10.1109/..
 
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3

A 50-Gb/s PAM-4 Receiver With Adaptive Phase-Shifting CDR i..:

Shim, Minkyo ; Roh, Seungha ; Lee, Yunhee...
IEEE Transactions on Circuits and Systems I: Regular Papers.  , 2024
Link: https://doi.org/10.1109/..
 
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4

A 48 Gb/s PAM-4 Receiver With Pre-Cursor Adjustable Baud-Ra..:

Jung, Woosong ; Lee, Kwangho ; Park, Kwanseo...
IEEE Journal of Solid-State Circuits.  58 (2023)  5 - p. 1414-1424 , 2023
Link: https://doi.org/10.1109/..
 
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5

A 1.1-pJ/b 8-to-16-Gb/s Receiver With Stochastic CTLE Adapt..:

Shim, Minkyo ; Lee, Kwang-Hoon ; Roh, Seungha..
IEEE Transactions on Circuits and Systems II: Express Briefs.  70 (2023)  2 - p. 381-385 , 2023
Link: https://doi.org/10.1109/..
 
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6

A 12-Gbps, 0.24-pJ/b/dB PAM-4 Receiver With Dead-Zone Free ..:

Shim, Minkyo ; Lee, Woonghee ; Lee, Yunhee..
IEEE Access.  11 (2023)  - p. 46513-46521 , 2023
Link: https://doi.org/10.1109/..
 
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7

Design Techniques for 48-Gb/s 2.4-pJ/b PAM-4 Baud-Rate CDR ..:

Ju, Haram ; Lee, Kwangho ; Park, Kwanseo..
IEEE Journal of Solid-State Circuits.  57 (2022)  10 - p. 3014-3024 , 2022
Link: https://doi.org/10.1109/..
 
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8

A 200Gb/s PAM-4 Transmitter with Hybrid Sub-Sampling PLL in..:

, In: 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits),
Wang, Zhongkai ; Choi, Minsoo ; Kwon, Paul... - p. 34-35 , 2022
Link: https://doi.org/10.1109/..
 
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9

An Output Bandwidth Optimized 200-Gb/s PAM-4 100-Gb/s NRZ T..:

Wang, Zhongkai ; Choi, Minsoo ; Lee, Kyoungtae...
IEEE Journal of Solid-State Circuits.  57 (2022)  1 - p. 21-31 , 2022
Link: https://doi.org/10.1109/..
 
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10

Design Techniques for a 6.4–32-Gb/s 0.96-pJ/b Continuous-Ra..:

Park, Kwanseo ; Shim, Minkyo ; Ko, Han-Gon..
IEEE Journal of Solid-State Circuits.  57 (2022)  2 - p. 573-585 , 2022
Link: https://doi.org/10.1109/..
 
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11

A 10 Gb/s PAM-4 Transmitter With Feed-Forward Implementatio..:

Kang, Byungjun ; Jeong, Gyu-Seob ; Hwang, Jeongho...
IEEE Access.  9 (2021)  - p. 156789-156798 , 2021
Link: https://doi.org/10.1109/..
 
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12

6.7 An 8Gb/s/µm FFE-Combined Crosstalk-Cancellation Scheme ..:

, In: 2020 IEEE International Solid- State Circuits Conference - (ISSCC),
Ko, Han-Gon ; Shin, Soyeong ; Oh, Jonghyun.. - p. 128-130 , 2020
Link: https://doi.org/10.1109/..
 
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13

Analysis of frequency detection capability of Alexander pha..:

Park, Kwanseo ; Jeong, Deog‐Kyoon
Electronics Letters.  56 (2020)  4 - p. 180-182 , 2020
Link: https://doi.org/10.1049/..
 
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14

6.5 A 6.4-to-32Gb/s 0.96pJ/b Referenceless CDR Employing ML..:

, In: 2020 IEEE International Solid- State Circuits Conference - (ISSCC),
Park, Kwanseo ; Shim, Minkyo ; Ko, Han-Gon. - p. 124-126 , 2020
Link: https://doi.org/10.1109/..
 
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15

A 64Gb/s 2.29pJ/b PAM-4 VCSEL Transmitter With 3-Tap Asymme..:

Hwang, Jeongho ; Choi, Hong-Seok ; Do, Hyungrok...
2019 SYMPOSIUM ON VLSI CIRCUITS, pp.C268-C269.  , 2022
Link: https://hdl.handle.net/1..
 
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