Pineda de Gyvez, José
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1

Twenty Years of Near/Sub-Threshold Design Trends and Enable..:

Singh, Kamlesh ; Pineda de Gyvez, Jose
IEEE Transactions on Circuits and Systems II: Express Briefs.  68 (2021)  1 - p. 5-11 , 2021
 
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2

Keyword Spotting using Time-Domain Features in a Temporal C..:

, In: 2019 22nd Euromicro Conference on Digital System Design (DSD),
Ibrahim, Emad A. ; Huisken, Jos ; Fatemi, Hamed. - p. 313-319 , 2019
 
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3

Timing Speculation With Optimal In Situ Monitoring Placemen..:

Ahmadi Balef, Hadi ; Fatemi, Hamed ; Goossens, Kees.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  27 (2019)  5 - p. 1206-1217 , 2019
 
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5

Effective In-Situ Chip Health Monitoring with Selective Mon..:

, In: Proceedings of the 2018 Great Lakes Symposium on VLSI,
 
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6

Reconfigurable Support Vector Machine Classifier with Appro..:

, In: 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI),
Van Leussen, Martin ; Huisken, Jos ; Wang, Lei.. - p. 13-18 , 2017
 
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7

Logic Design Partitioning for Stacked Power Domains:

Blutman, Kristof ; Fatemi, Hamed ; Kapoor, Ajay...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  25 (2017)  11 - p. 3045-3056 , 2017
 
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8

An Improved Methodology for Resilient Design Implementation:

Kahng, Andrew B. ; Kang, Seokhyeong ; Li, Jiajia.
ACM Transactions on Design Automation of Electronic Systems.  20 (2015)  4 - p. 1-26 , 2015
 
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9

A 13 bits 4.096 GHz 45 nm CMOS digital decimation filter ch..:

Huang, Yanxiang ; Kapoor, Ajay ; Rutten, Robert.
Microprocessors and Microsystems.  39 (2015)  8 - p. 869-878 , 2015
 
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10

An Improved Methodology for Resilient Design Implementation:

Kahng, Andrew B. ; Kang, Seokhyeong ; Li, Jiajia.
ACM Transactions on Design Automation of Electronic Systems (TODAES).  20 (2015)  4 - p. 1-26 , 2015
 
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11

Body-Bias-Driven Design Strategy for Area- and Performance-..:

Meijer, Maurice ; Pineda de Gyvez, José
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  20 (2012)  1 - p. 42-51 , 2012
 
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12

Low-power high-resolution analog to digital converters 

design, test and calibration  Analog circuits and signal processing
Copies:  Zentrale:E02 a elt 943 e/088
 
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13

A 1.2v 55mW 12bits self-calibrated dual-residue analog to d..:

, In: Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design,
Zjajo, Amir ; Pineda de Gyvez, Jose - p. 187-192 , 2011
 
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14

An Ultra-Low-Energy Multi-Standard JPEG Co-Processor in 65 ..:

Pu, Yu ; Pineda de Gyvez, Jose ; Corporaal, Henk.
IEEE Journal of Solid-State Circuits.  45 (2010)  3 - p. 668-680 , 2010
 
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