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Pontikakis, Bill
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1

DR-PIFO: A Dynamic Ranking Packet Scheduler Using a Push-In..:

Elbediwy, Mostafa ; Pontikakis, Bill ; Ghaffari, Alireza..
IEEE Transactions on Network and Service Management.  21 (2024)  1 - p. 355-371 , 2024
Link: https://doi.org/10.1109/..
 
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2

A Hardware Architecture of a Dynamic Ranking Packet Schedul..:

Elbediwy, Mostafa ; Pontikakis, Bill ; David, Jean-Pierre.
IEEE Access.  11 (2023)  - p. 61422-61436 , 2023
Link: https://doi.org/10.1109/..
 
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3

An FPGA-based HW/SW Co-Verification Environment for Program..:

, In: 2022 IEEE International Symposium on Circuits and Systems (ISCAS),
Su, Mengyue ; David, Jean-Pierre ; Savaria, Yvon.. - p. 2529-2533 , 2022
Link: https://doi.org/10.1109/..
 
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4

A Low-Complexity High-Speed Clock Generator for Dynamic Fre..:

, In: 2007 IEEE International Symposium on Circuits and Systems (ISCAS),
Pontikakis, Bill ; Bui, Hung Tien ; Boyer, Francois-Raymond. - p. None , 2007
Link: https://doi.org/10.1109/..
 
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5

A Hardware Architecture of a Dynamic Ranking Packet Schedul..:

Elbediwy, Mostafa ; Pontikakis, Bill ; David, Jean Pierre.
https://publications.polymtl.ca/54804/1/2023_Elbediwy_Hardware_Architecture_Dynamic_Ranking__Packet.pdf.  , 2023
Link: https://publications.pol..
 
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6

A Hardware Architecture of a Dynamic Ranking Packet Schedul..:

Mostafa Elbediwy ; Bill Pontikakis ; Jean-Pierre David.
https://ieeexplore.ieee.org/document/10153594/.  , 2023
Link: https://doi.org/10.1109/..
 
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