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Riedel, Samuel
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1

Hier-3D: A Methodology for Physical Hierarchy Exploration o..:

Bethur, Nesara Eranna ; Agnesina, Anthony ; Brunion, Moritz...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.  43 (2024)  7 - p. 1957-1970 , 2024
Link: https://doi.org/10.1109/..
 
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2

TeraPool-SDR: An 1.89TOPS 1024 RV-Cores 4MiB Shared-L1 Clus..:

, In: Proceedings of the Great Lakes Symposium on VLSI 2024,
Zhang, Yichao ; Bertuletti, Marco ; Riedel, Samuel... - p. 86-91 , 2024
Link: https://dl.acm.org/doi/1..
 
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3

3D Partitioning with Pipeline Optimization for Low-Latency ..:

, In: 2024 IEEE International Symposium on Circuits and Systems (ISCAS),
Das, Sudipta ; Riedel, Samuel ; Bertuletti, Marco... - p. 1-5 , 2024
Link: https://doi.org/10.1109/..
 
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4

A High-Performance, Energy-Efficient Modular DMA Engine Arc..:

Benz, Thomas ; Rogenmoser, Michael ; Scheffler, Paul...
IEEE Transactions on Computers.  73 (2024)  1 - p. 263-277 , 2024
Link: https://doi.org/10.1109/..
 
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5

Enabling Efficient Hybrid Systolic Computation in Shared-L1..:

Mazzola, Sergio ; Riedel, Samuel ; Benini, Luca
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  , 2024
Link: https://doi.org/10.1109/..
 
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6

MemPool: A Scalable Manycore Architecture With a Low-Latenc..:

Riedel, Samuel ; Cavalcante, Matheus ; Andri, Renzo.
IEEE Transactions on Computers.  72 (2023)  12 - p. 3561-3575 , 2023
Link: https://doi.org/10.1109/..
 
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7

Fast Shared-Memory Barrier Synchronization for a 1024-Cores..:

, In: Lecture Notes in Computer Science; Embedded Computer Systems: Architectures, Modeling, and Simulation,
Bertuletti, Marco ; Riedel, Samuel ; Zhang, Yichao.. - p. 241-254 , 2023
Link: https://doi.org/10.1007/..
 
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8

MinPool: A 16-core NUMA-L1 Memory RISC-V Processor Cluster ..:

, In: 2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS),
Riedel, Samuel ; Cavalcante, Matheus ; Frouzakis, Manos... - p. 1-4 , 2023
Link: https://doi.org/10.1109/..
 
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9

MemPool Meets Systolic: Flexible Systolic Computation in a ..:

, In: 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE),
Riedel, Samuel ; Khov, Gua Hao ; Mazzola, Sergio... - p. 1-2 , 2023
Link: https://doi.org/10.23919..
 
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10

Hier-3D: A Hierarchical Physical Design Methodology for Fac..:

, In: Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design,
Agnesina, Anthony ; Brunion, Moritz ; Garcia-Ortiz, Alberto... - p. 1-6 , 2022
Link: https://dl.acm.org/doi/1..
 
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11

Spatz : A Compact Vector Processing Unit for High-Perfor..:

, In: Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design,
Cavalcante, Matheus ; Wüthrich, Domenic ; Perotti, Matteo.. - p. 1-9 , 2022
Link: https://dl.acm.org/doi/1..
 
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12

Banshee: A Fast LLVM-Based RISC-V Binary Translator:

, In: 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD),
Riedel, Samuel ; Schuiki, Fabian ; Scheffler, Paul.. - p. 1-9 , 2021
Link: https://doi.org/10.1109/..
 
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13

ATUNs: Modular and Scalable Support for Atomic Operations i..:

, In: 2020 57th ACM/IEEE Design Automation Conference (DAC),
Kurth, Andreas ; Riedel, Samuel ; Zaruba, Florian.. - p. 1-6 , 2020
Link: https://doi.org/10.1109/..
 
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14

ATUNs : modular and scalable support for atomic operatio..:

, In: Proceedings of the 57th ACM/EDAC/IEEE Design Automation Conference,
Kurth, Andreas ; Riedel, Samuel ; Zaruba, Florian.. - p. 1-6 , 2020
Link: https://dl.acm.org/doi/1..
 
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15

MinPool: A 16-core NUMA-L1 Memory RISC-V Processor Cluster ..:

Riedel, Samuel ; id_orcid:0 000-0002-5772-6377 ; Cavalcante, Matheus...
info:eu-repo/semantics/altIdentifier/doi/10.1109/icecs58634.2023.10382925.  , 2024
Link: https://hdl.handle.net/2..
 
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