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Ryu, Sigang
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1

Fractionally-Spaced Equalizers as Clock and Data Recovery L..:

Ryu, Sigang ; Kim, Jaeha ; Raychowdhury, Arijit
IEEE Transactions on Circuits and Systems I: Regular Papers.  71 (2024)  7 - p. 3002-3015 , 2024
Link: https://doi.org/10.1109/..
 
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2

30.1 A 40nm VLIW Edge Accelerator with 5MB of 0.256pJ/b RRA..:

, In: 2024 IEEE International Solid-State Circuits Conference (ISSCC),
Spetalnick, Samuel D. ; Lele, Ashwin Sanjay ; Crafton, Brian... - p. 482-484 , 2024
Link: https://doi.org/10.1109/..
 
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3

A Modular, Distributed and Scalable DOA Estimator for MIMO ..:

, In: 2024 IEEE/MTT-S International Microwave Symposium - IMS 2024,
Assoa, Adou Sangbone ; Bhat, Ashwin ; Ryu, Sigang. - p. 90-93 , 2024
Link: https://doi.org/10.1109/..
 
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4

A 65nm 60mW Dual-Loop Adaptive Digital Beamformer with Opti..:

, In: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits),
Ryu, Sigang ; Assoa, Adou Sangbone ; Konno, Shota. - p. 1-2 , 2023
Link: https://doi.org/10.23919..
 
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5

A Scalable Platform for Single-Snapshot Direction Of Arriva..:

, In: Proceedings of the Great Lakes Symposium on VLSI 2023,
Assoa, Adou Sangbone ; Bhat, Ashwin ; Ryu, Sigang. - p. 631-637 , 2023
Link: https://dl.acm.org/doi/1..
 
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