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SHI, Youhua
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1

An Efficient Multiplier-less Processing Element on Power-of..:

Li, Jiaxiang ; Yanagisawa, Masao ; Shi, Youhua
Integrated Circuits and Systems.  , 2024
Link: https://doi.org/10.23919..
 
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2

A Dual-Output Rectifier-Based Self-Powered Interface Circui..:

Su, Yirui ; Yanagisawa, Masao ; Shi, Youhua
IEEE Transactions on Power Electronics.  39 (2024)  6 - p. 6630-6634 , 2024
Link: https://doi.org/10.1109/..
 
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3

An Area-Power-Efficient Multiplier-less Processing Element ..:

, In: 2023 IEEE 15th International Conference on ASIC (ASICON),
Li, Jiaxiang ; Yanagisawa, Masao ; Shi, Youhua - p. 1-4 , 2023
Link: https://doi.org/10.1109/..
 
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4

Strategy for Improving Cycle of Maximized Energy Output of ..:

, In: 2023 International Conference on IC Design and Technology (ICICDT),
Su, Yirui ; Yanagisawa, Masao ; Shi, Youhua - p. 131-135 , 2023
Link: https://doi.org/10.1109/..
 
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5

Dataflow Optimization through Exploring Single-Layer and In..:

Ye, Jinghao ; Yanagisawa, Masao ; Shi, Youhua
Electronics.  11 (2022)  15 - p. 2356 , 2022
Link: https://doi.org/10.3390/..
 
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6

Scalable Hardware Efficient Architecture for Parallel FIR F..:

Ye, Jinghao ; Yanagisawa, Masao ; Shi, Youhua
Electronics.  11 (2022)  20 - p. 3272 , 2022
Link: https://doi.org/10.3390/..
 
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7

Power-Efficient Deep Convolutional Neural Network Design Th..:

Ye, Lin ; Ye, Jinghao ; Yanagisawa, Masao.
IEEE Access.  9 (2021)  - p. 17411-17420 , 2021
Link: https://doi.org/10.1109/..
 
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8

Faithfully Truncated Adder-Based Area-Power Efficient FIR D..:

YE, Jinghao ; YANAGISAWA, Masao ; SHI, Youhua
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences.  E103.A (2020)  9 - p. 1063-1070 , 2020
Link: https://doi.org/10.1587/..
 
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9

A High-Performance Symmetric Hybrid Form Design for High-Or..:

, In: 2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS),
Ye, Jinghao ; Yanagisawa, Masao ; Shi, Youhua - p. 121-124 , 2020
Link: https://doi.org/10.1109/..
 
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10

A Power-Efficient Soft Error Hardened Latch Design with In-..:

, In: 2019 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia),
Tajima, Saki ; Yanagisawa, Masao ; Shi, Youhua - p. 53-56 , 2019
Link: https://doi.org/10.1109/..
 
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11

A Zero-Gating Processing Element Design for Low-Power Deep ..:

, In: 2019 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS),
Ye, Lin ; Ye, Jinghao ; Yanagisawa, Masao. - p. 317-320 , 2019
Link: https://doi.org/10.1109/..
 
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12

A Bit-Segmented Adder Chain based Symmetric Transpose Two-B..:

, In: 2019 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS),
Ye, Jinghao ; Yanagisawa, Masao ; Shi, Youhua - p. 29-32 , 2019
Link: https://doi.org/10.1109/..
 
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13

An Adder-Segmentation-based FIR for High Speed Signal Proce..:

, In: 2019 IEEE 13th International Conference on ASIC (ASICON),
Ye, Jinghao ; Yanagisawa, Masao ; Shi, Youhua - p. 1-4 , 2019
Link: https://doi.org/10.1109/..
 
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14

Extension and Performance/Accuracy Formulation for Optimal ..:

HAYAMIZU, Ken ; TOGAWA, Nozomu ; YANAGISAWA, Masao.
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences.  E101.A (2018)  7 - p. 1014-1024 , 2018
Link: https://doi.org/10.1587/..
 
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15

A Low Power Soft Error Hardened Latch with Schmitt-Trigger-..:

TAJIMA, Saki ; TOGAWA, Nozomu ; YANAGISAWA, Masao.
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences.  E101.A (2018)  7 - p. 1025-1034 , 2018
Link: https://doi.org/10.1587/..
 
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