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Saiz-Adalid, Luis-J.
26  results:
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1

A Proposal of an ECC-based Adaptive Fault-Tolerant Mechanis..:

Gracia-Morán, Joaquín ; Saiz-Adalid, Luis-J. ; Baraza-Calvo, J.-Carlos..
IEEE Latin America Transactions.  22 (2024)  5 - p. 418-427 , 2024
Link: https://doi.org/10.1109/..
 
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2

Proposal of an Adaptive Fault Tolerance Mechanism to Tolera..:

Baraza-Calvo, J.-Carlos ; Gracia-Morán, Joaquín ; Saiz-Adalid, Luis-J...
Electronics.  9 (2020)  12 - p. 2074 , 2020
Link: https://doi.org/10.3390/..
 
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3

Reducing the Overhead of BCH Codes: New Double Error Correc..:

Saiz-Adalid, Luis-J. ; Gracia-Morán, Joaquín ; Gil-Tomás, Daniel..
Electronics.  9 (2020)  11 - p. 1897 , 2020
Link: https://doi.org/10.3390/..
 
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4

Ultrafast Codes for Multiple Adjacent Error Correction and ..:

Saiz-Adalid, Luis-J. ; Gracia-Moran, Joaquin ; Gil-Tomas, Daniel..
IEEE Access.  7 (2019)  - p. 151131-151143 , 2019
Link: https://doi.org/10.1109/..
 
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5

MCU Tolerance in SRAMs Through Low-Redundancy Triple Adjace..:

Saiz-Adalid, Luis-J. ; Reviriego, Pedro ; Gil, Pedro..
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  23 (2015)  10 - p. 2332-2336 , 2015
Link: https://doi.org/10.1109/..
 
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6

Ultrafast Single Error Correction Codes for Protecting Proc..:

, In: 2015 11th European Dependable Computing Conference (EDCC),
Saiz-Adalid, Luis-J. ; Gil, Pedro ; Gracia-Moran, Joaquin.. - p. 144-154 , 2015
Link: https://doi.org/10.1109/..
 
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7

Studying the effects of intermittent faults on a microcontr..:

Gil-Tomás, Daniel ; Gracia-Morán, Joaquín ; Baraza-Calvo, J.-Carlos..
Microelectronics Reliability.  52 (2012)  11 - p. 2837-2846 , 2012
Link: https://doi.org/10.1016/..
 
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8

Analyzing the Impact of Intermittent Faults on Microprocess..:

Gil-Tomas, Daniel ; Gracia-Moran, Joaquin ; Baraza-Calvo, J.-Carlos..
IEEE Design & Test of Computers.  29 (2012)  6 - p. 66-73 , 2012
Link: https://doi.org/10.1109/..
 
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9

Design, Implementation and Evaluation of a Low Redundant Er..:

Gracia-Morán, Joaquín ; Saiz-Adalid, Luis-J ; Baraza-Calvo, Juan-Carlos..
info:eu-repo/grantAgreement/UPV//200190032/.  , 2021
Link: http://hdl.handle.net/10..
 
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10

Reducing the Overhead of BCH Codes: New Double Error Correc..:

Saiz-Adalid, Luis-J ; Gracia-Morán, Joaquín ; Gil Tomás, Daniel Antonio..
Electronics.  , 2020
Link: http://hdl.handle.net/10..
 
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11

Proposal of an Adaptive Fault Tolerance Mechanism to Tolera..:

Baraza Calvo, Juan Carlos ; Gracia-Morán, Joaquín ; Saiz-Adalid, Luis-J..
Electronics.  , 2020
Link: http://hdl.handle.net/10..
 
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12

Fault Modeling of Graphene Nanoribbon FET Logic Circuits:

Gil Tomás, Daniel Antonio ; Gracia-Morán, Joaquín ; Saiz-Adalid, Luis-J.
Electronics.  , 2019
Link: http://hdl.handle.net/10..
 
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13

Ultrafast Codes for Multiple Adjacent Error Correction and ..:

Saiz-Adalid, Luis-J ; Gracia-Morán, Joaquín ; Gil Tomás, Daniel Antonio..
IEEE Access.  , 2019
Link: http://hdl.handle.net/10..
 
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14

Improving Error Correction Codes for Multiple-Cell Upsets i..:

Gracia-Morán, Joaquín ; Saiz-Adalid, Luis-J ; Gil Tomás, Daniel Antonio.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  , 2018
Link: http://hdl.handle.net/10..
 
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15

MCU Tolerance in SRAMs through Low Redundancy Triple Adjace..:

Saiz-Adalid, Luis-J ; Reviriego, Pedro ; Gil, Pedro..
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  , 2015
Link: http://hdl.handle.net/10..
 
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