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Saligram, Rakshith
15  results:
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1

Cool-CIM: Cryogenic Operation of Analog Compute-In-Memory f..:

, In: 2023 International Electron Devices Meeting (IEDM),
Wang, Wei-Chun ; Saligram, Rakshith ; Sharma, Sudarshan... - p. 1-4 , 2023
Link: https://doi.org/10.1109/..
 
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2

Design Exploration of 14 nm FinFET for Energy-Efficient Cry..:

Gaidhane, Amol D. ; Saligram, Rakshith ; Chakraborty, Wriddhi...
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits.  9 (2023)  2 - p. 108-115 , 2023
Link: https://doi.org/10.1109/..
 
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3

Cryogenic CMOS as an Enabler for Low Power Dynamic Logic:

, In: 2023 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED),
Saligram, Rakshith ; Datta, Suman ; Raychowdhury, Arijit - p. 1-6 , 2023
Link: https://doi.org/10.1109/..
 
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4

Design Space Exploration of Interconnect Materials for Cryo..:

Saligram, Rakshith ; Datta, Suman ; Raychowdhury, Arijit
IEEE Transactions on Circuits and Systems I: Regular Papers.  69 (2022)  11 - p. 4610-4618 , 2022
Link: https://doi.org/10.1109/..
 
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5

Power Performance Analysis of Digital Standard Cells for 28..:

Saligram, Rakshith ; Chakraborty, Wriddhi ; Cao, Ningyuan...
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits.  7 (2021)  2 - p. 193-200 , 2021
Link: https://doi.org/10.1109/..
 
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6

Characterization and Modeling of 22 nm FDSOI Cryogenic RF C..:

Chakraborty, Wriddhi ; Aabrar, Khandker Akif ; Gomez, Jorge...
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits.  7 (2021)  2 - p. 184-192 , 2021
Link: https://doi.org/10.1109/..
 
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7

Multilevel Signaling for High-Speed Chiplet-to-Chiplet Comm..:

, In: VLSI-SoC: Design Trends; IFIP Advances in Information and Communication Technology,
Saligram, Rakshith ; Kaul, Ankit ; Bakir, Muhannad S.. - p. 149-178 , 2021
Link: https://doi.org/10.1007/..
 
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8

Pseudo-Static 1T Capacitorless DRAM using 22nm FDSOI for Cr..:

, In: 2021 IEEE International Electron Devices Meeting (IEDM),
Chakraborty, Wriddhi ; Saligram, Rakshith ; Gupta, Aniket... - p. 40.1.1-40.1.4 , 2021
Link: https://doi.org/10.1109/..
 
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9

A Model Study of Multilevel Signaling for High-Speed Chiple..:

, In: 2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration (VLSI-SOC),
Saligram, Rakshith ; Kaul, Ankit ; Bakir, Muhannad S. - p. 159-164 , 2020
Link: https://doi.org/10.1109/..
 
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10

Design of Parity Preserving Logic Based Fault Tolerant Reve..:

Saligram, Rakshith ; Hegde, Shrihari Shridhar ; Kulkarni, Shashidhar A..
http://arxiv.org/abs/1307.3690.  , 2013
Link: http://arxiv.org/abs/130..
 
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11

Design Exploration of 14 nm FinFET for Energy-Efficient Cry..:

Amol D. Gaidhane ; Rakshith Saligram ; Wriddhi Chakraborty...
https://ieeexplore.ieee.org/document/10310237/.  , 2023
Link: https://doi.org/10.1109/..
 
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12

Power Performance Analysis of Digital Standard Cells for 28..:

Rakshith Saligram ; Wriddhi Chakraborty ; Ningyuan Cao...
https://ieeexplore.ieee.org/document/9627705/.  , 2021
Link: https://doi.org/10.1109/..
 
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13

Characterization and Modeling of 22 nm FDSOI Cryogenic RF C..:

Wriddhi Chakraborty ; Khandker Akif Aabrar ; Jorge Gomez...
https://ieeexplore.ieee.org/document/9627653/.  , 2021
Link: https://doi.org/10.1109/..
 
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14

DESIGN OF PARITY PRESERVING LOGIC BASED FAULT TOLERANT REVE..:

Rakshith Saligram ; Shrihari Shridhar Hegde ; Shashidhar A Kulkarni..
doi:10.5281/zenodo.3342583.  , 2019
Link: https://zenodo.org/recor..
 
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15

DESIGN OF REVERSIBLE MULTIPLIERS FOR LINEAR FILTERING APPLI..:

Rakshith Saligram ; Rakshith T.R
https://zenodo.org/record/2642005.  , 2012
Link: https://zenodo.org/recor..
 
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