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1

Securator: A Fast and Secure Neural Processing Unit:

, In: 2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA),

Shrivastava, Nivedita ; Sarangi, Smruti Ranjan - p. 1127-1139 , 2023

Link: https://doi.org/10.1109/..

2

Perspectives on Teaching Computer Architecture in Developin..:

, In: Proceedings of the 15th Annual ACM India Compute Conference,

Sarangi, Smruti Ranjan - p. 7 ff. , 2022

Link: https://dl.acm.org/doi/1..

3

A survey of hardware architectures for generative adversari..:

Shrivastava, Nivedita ; Hanif, Muhammad Abdullah ; Mittal, Sparsh..
Journal of Systems Architecture. 118 (2021) - p. 102227 , 2021

Link: https://doi.org/10.1016/..

4

SecONet: A Security Framework for a Photonic Network-on-Chi:

, In: 2020 14th IEEE/ACM International Symposium on Networks-on-Chip (NOCS),

Bashir, Janibul ; Goodchild, Chandran ; Sarangi, Smruti Ranjan - p. 1-8 , 2020

Link: https://doi.org/10.1109/..

5

Predict, Share, and Recycle Your Way to Low-power Nanophoto..:

Bashir, Janibul ; Sarangi, Smruti Ranjan
ACM Journal on Emerging Technologies in Computing Systems. 16 (2019) 1 - p. 1-26 , 2019

Link: https://doi.org/10.1145/..

6

Predict, Share, and Recycle Your Way to Low-power Nanophoto..:

Bashir, Janibul ; Sarangi, Smruti Ranjan
ACM Journal on Emerging Technologies in Computing Systems (JETC). 16 (2019) 1 - p. 1-26 , 2019

Link: https://dl.acm.org/doi/1..

7

PC-ILP: A Fast and Intuitive Method to Place Electric Vehic..:

Bose, Mehul ; Dutta, Bivas Ranjan ; Shrivastava, Nivedita.
Smart Cities. 6 (2023) 6 - p. 3060-3092 , 2023

Link: https://doi.org/10.3390/..

8

Reusing Trace Buffers as Victim Caches:

Jindal, Neetu ; Panda, Preeti Ranjan ; Sarangi, Smruti R.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 26 (2018) 9 - p. 1699-1712 , 2018

Link: https://doi.org/10.1109/..

9

Managing Trace Summaries to Minimize Stalls During Postsili..:

Chandran, Sandeep ; Panda, Preeti Ranjan ; Sarangi, Smruti R....
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25 (2017) 6 - p. 1881-1894 , 2017

Link: https://doi.org/10.1109/..

10

Area-Aware Cache Update Trackers for Postsilicon Validation:

Chandran, Sandeep ; Sarangi, Smruti R. ; Panda, Preeti Ranjan
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 24 (2016) 5 - p. 1794-1807 , 2016

Link: https://doi.org/10.1109/..

11

Space sensitive cache dumping for post-silicon validation:

, In: Proceedings of the Conference on Design, Automation and Test in Europe,

Chandran, Sandeep ; Sarangi, Smruti R. ; Panda, Preeti Ranjan - p. 497-502 , 2013

Link: https://dl.acm.org/doi/1..

12

Semantic-Aided Image Transmission System with Unequal Error..:

, In: 2024 IEEE Wireless Communications and Networking Conference (WCNC),

Fayaz, Nargis ; Shreshtha, Aman ; Sarangi, Smruti.. - p. 01-06 , 2024

Link: https://doi.org/10.1109/..

13

Fundamental Results for a Generic Implementation of Barrier..:

Chandran, Sandeep ; Peter, Eldhose ; Panda, Preeti Ranjan.
http://arxiv.org/abs/1510.00220. , 2015

Link: http://arxiv.org/abs/151..

14

Assessing ChatGPT's Proficiency in Simplifying Radiological..:

Sarangi, Pradosh Kumar ; Lumbani, Amrita ; Swarup, M Sarthak...
Cureus. , 2023

Link: https://doi.org/10.7759/..

15

PC-ILP: A Fast and Intuitive Method to Place Electric Vehic..:

Mehul Bose ; Bivas Ranjan Dutta ; Nivedita Shrivastava.
https://www.mdpi.com/2624-6511/6/6/137. , 2023

Link: https://doi.org/10.3390/..

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