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Schiavone, Pasquale D
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1

X-HEEP : An Open-Source, Configurable and Extendible RIS..:

, In: Proceedings of the 20th ACM International Conference on Computing Frontiers,
Schiavone, Pasquale Davide ; Machetti, Simone ; Peón-Quirós, Miguel... - p. 379-380 , 2023
Link: https://dl.acm.org/doi/1..
 
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2

Arnold: An eFPGA-Augmented RISC-V SoC for Flexible and Low-..:

Schiavone, Pasquale Davide ; Rossi, Davide ; Di Mauro, Alfio...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  29 (2021)  4 - p. 677-690 , 2021
Link: https://doi.org/10.1109/..
 
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3

Neuro-PULP: A Paradigm Shift Towards Fully Programmable Pla..:

, In: 2020 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS),
Schiavone, Pasquale Davide ; Rossi, Davide ; Liu, Yan... - p. 50-54 , 2020
Link: https://doi.org/10.1109/..
 
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4

On-line Testing for Autonomous Systems driven by RISC-V Pro..:

, In: 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT),
Ruospo, Annachiara ; Cantoro, Riccardo ; Sanchez, Ernesto... - p. 1-6 , 2019
Link: https://doi.org/10.1109/..
 
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5

Pushing On-chip Memories Beyond Reliability Boundaries in M..:

, In: 2019 IEEE International Electron Devices Meeting (IEDM),
Mauro, Alfio Di ; Conti, Francesco ; Schiavone, Pasquale Davide.. - p. 30.4.1-30.4.4 , 2019
Link: https://doi.org/10.1109/..
 
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6

XNOR Neural Engine: A Hardware Accelerator IP for 21.6-fJ/o..:

Conti, Francesco ; Schiavone, Pasquale Davide ; Benini, Luca
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.  37 (2018)  11 - p. 2940-2951 , 2018
Link: https://doi.org/10.1109/..
 
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7

A sensor fusion approach for drowsiness detection in wearab..:

Kartsch, Victor Javier ; Benatti, Simone ; Schiavone, Pasquale Davide..
Information Fusion.  43 (2018)  - p. 66-76 , 2018
Link: https://doi.org/10.1016/..
 
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8

Near-Threshold RISC-V Core With DSP Extensions for Scalable..:

Gautschi, Michael ; Schiavone, Pasquale Davide ; Traber, Andreas...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  25 (2017)  10 - p. 2700-2713 , 2017
Link: https://doi.org/10.1109/..
 
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9

HW/SW approaches for RISC-V code size reduction:

Perotti, Matteo ; Schiavone, Pasquale D ; Tagliavini, Giuseppe...
http://hdl.handle.net/20.500.11850/461404.  , 2020
Link: https://hdl.handle.net/2..
 
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10

An Open-Source Verification Framework for Open-Source Cores..:

Schiavone, Pasquale D ; Sanchez, Ernesto ; Ruospo, Annachiara...
info:eu-repo/semantics/altIdentifier/doi/10.1109/VLSI-SoC.2018.8644818.  , 2018
Link: https://hdl.handle.net/2..
 
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11

Quentin: an Ultra-Low-Power PULPissimo SoC in 22nm FDX:

Schiavone, Pasquale D ; Rossi, Davide ; Pullini, Antonio...
info:eu-repo/semantics/altIdentifier/doi/10.1109/S3S.2018.8640145.  , 2018
Link: https://hdl.handle.net/2..
 
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12

XNOR Neural Engine: a Hardware Accelerator IP for 21.6 fJ/o..:

Conti, Francesco ; Schiavone, Pasquale D ; Benini, Luca.
info:eu-repo/semantics/altIdentifier/doi/10.1109/TCAD.2018.2857019.  , 2018
Link: https://hdl.handle.net/2..
 
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13

RISC-V Meets 22FDX: an Open Source Ultra-low Power Microcon..:

Schiavone, Pasquale ; Charagulla, Sanjay ; Teepe, Gerd...
http://hdl.handle.net/20.500.11850/311769.  , 2018
Link: https://hdl.handle.net/2..
 
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14

Fast and Accurate Multiclass Inference for MI-BCIs Using La..:

Hersche, Michael ; Rellstab, Tino ; Schiavone, Pasquale D...
info:eu-repo/semantics/altIdentifier/doi/10.23919/EUSIPCO.2018.8553378.  , 2018
Link: https://hdl.handle.net/2..
 
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15

X-HEEP: An Open-Source, Configurable and Extendible RISC-V ..:

Machetti, Simone ; Schiavone, Pasquale Davide ; Müller, Thomas Christoph..
http://arxiv.org/abs/2401.05548.  , 2024
Link: http://arxiv.org/abs/240..
 
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