Schram, T.
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2

Towards low damage and fab-compatible top-contacts in MX2 t..:

, In: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits),
Kundu, S. ; van Dorp, D. H. ; Schram, T.... - p. 1-2 , 2023
 
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3

Impact of gate stack processing on the hysteresis of 300 mm..:

, In: 2023 IEEE International Reliability Physics Symposium (IRPS),
Panarella, L. ; Kaczer, B. ; Smets, Q.... - p. 1-6 , 2023
 
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4

Integration of epitaxial monolayer MX₂ channels on 300mm wa..:

, In: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits),
Ghosh, S. ; Smets, Q. ; Banerjee, S.... - p. 1-2 , 2023
 
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5

Exploring manufacturability of novel 2D channel materials: ..:

, In: 2023 International Electron Devices Meeting (IEDM),
Dorow, C. J. ; Schram, T. ; Smets, Q.... - p. 1-4 , 2023
 
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6

Scaled FinFETs Connected by Using Both Wafer Sides for Rout..:

, In: 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits),
Veloso, A. ; Jourdain, A. ; Radisic, D.... - p. 284-285 , 2022
 
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7

Analysis of BTI in 300 mm integrated dual-gate WS2 FETs:

, In: 2022 Device Research Conference (DRC),
Panarella, L. ; Smets, Q. ; Verreck, D.... - p. 1-2 , 2022
 
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8

Addressing Key Challenges for SiGe-pFin Technologies: Fin I..:

, In: 2020 IEEE Symposium on VLSI Technology,
Arimura, H. ; Capogreco, E. ; Wostyn, K.... - p. 1-2 , 2020
 
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10

Scaled transistors with 2D materials from the 300mm fab:

, In: 2020 IEEE Silicon Nanoelectronics Workshop (SNW),
Asselberghs, I. ; Schram, T. ; Smets, Q.... - p. 67-68 , 2020
 
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11

Virtual Process-Based Spacer & Junction Optimization for an..:

, In: 2020 4th IEEE Electron Devices Technology & Manufacturing Conference (EDTM),
Guissi, S. ; Schram, T. ; Schuddinck, P... - p. 1-4 , 2020
 
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12

Low frequency noise analysis on Si/SiGe superlattice I/O n-..:

, In: 2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS),
Boudier, D. ; Cretu, B. ; Simoen, E.... - p. 1-4 , 2019
 
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13

Low-Frequency Noise Assessment of Work Function Engineering..:

Claeys, C. ; Ritzenthaler, R. ; Schram, T....
ECS Journal of Solid State Science and Technology.  8 (2019)  2 - p. N25-N31 , 2019
 
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14

Can we optimize the gate oxide quality of DRAM input/output..:

Simoen, E ; O'Sullivan, B ; Ritzenthaler, R...
Semiconductor Science and Technology.  34 (2018)  1 - p. 015017 , 2018
 
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