Sigl, Georg
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3

A Masked Hardware Accelerator for Feed-Forward Neural Netwo..:

Brosch, Manuel ; Probst, Matthias ; Glaser, Matthias.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  32 (2024)  2 - p. 231-244 , 2024
 
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4

Hardware Honeypot: Setting Sequential Reverse Engineering o..:

, In: 2024 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS),
 
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5

The Impact of Hash Primitives and Communication Overhead fo..:

, In: Constructive Side-Channel Analysis and Secure Design; Lecture Notes in Computer Science,
Karl, Patrick ; Schupp, Jonas ; Sigl, Georg - p. 221-239 , 2024
 
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6

Fault-Simulation-Based Flip-Flop Classification for Reverse..:

, In: 2024 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS),
 
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7

Post-Quantum Signatures on RISC-V with Hardware Acceleratio:

Karl, Patrick ; Schupp, Jonas ; Fritzmann, Tim.
ACM Transactions on Embedded Computing Systems.  23 (2024)  2 - p. 1-23 , 2024
 
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8

DOMREP II:

, In: 2024 IEEE International Symposium on Hardware Oriented Security and Trust (HOST),
 
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12

FPGANeedle : Precise Remote Fault Attacks from FPGA to C..:

, In: Proceedings of the 28th Asia and South Pacific Design Automation Conference,
Gross, Mathieu ; Krautter, Jonas ; Gnad, Dennis... - p. 358-364 , 2023
 
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14

Timing Camouflage Enabled State Machine Obfuscation:

, In: 2022 IEEE Physical Assurance and Inspection of Electronics (PAINE),
 
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15

Toward a Human-Readable State Machine Extraction:

Brunner, Michaela ; Hepp, Alexander ; Baehr, Johanna.
ACM Transactions on Design Automation of Electronic Systems.  27 (2022)  6 - p. 1-31 , 2022
 
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