So, Byoungro
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1

Intel's Array Building Blocks : A retargetable, dynamic ..:

, In: Proceedings of the 9th Annual IEEE/ACM International Symposium on Code Generation and Optimization,
Newburn, Chris J. ; So, Byoungro ; Liu, Zhenying... - p. 224-235 , 2011
 
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2

Automatic mapping of C to FPGAs with the DEFACTO compilatio..:

Diniz, Pedro ; Hall, Mary ; Park, Joonseok..
Microprocessors and Microsystems.  29 (2005)  2-3 - p. 51-62 , 2005
 
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3

Optimizing Compiler for the CELL Processor:

, In: 14th International Conference on Parallel Architectures and Compilation Techniques (PACT'05),
Eichenbergert, Alexandre E. ; O'Brien, Kathryn ; O'Brien, Kevin... - p. 161,162,163,164,165,166,167,168,169,170,171,172 , 2005
 
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4

Custom Data Layout for Memory Parallelism:

, In: Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization,
So, Byoungro ; Hall, Mary W. ; Ziegler, Heidi E. - p. 291 ff. , 2004
 
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5

Using estimates from behavioral synthesis tools in compiler..:

, In: Proceedings of the 40th annual Design Automation Conference,
So, Byoungro ; Diniz, Pedro C. ; Hall, Mary W. - p. 514-519 , 2003
 
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6

A compiler approach to fast hardware design space explorati..:

, In: Proceedings of the ACM SIGPLAN 2002 conference on Programming language design and implementation,
So, Byoungro ; Hall, Mary W. ; Diniz, Pedro C. - p. 165-176 , 2002
 
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9

Measuring the effectiveness of automatic parallelization in..:

, In: Proceedings of the 12th international conference on Supercomputing,
So, Byoungro ; Moon, Sungdo ; Hall, Mary W. - p. 212-219 , 1998
 
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