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Spessot, Alessio
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1

Compact Physics Hot-Carrier Degradation Model Valid over a ..:

Tyaginov, Stanislav ; Bury, Erik ; Grill, Alexander...
Micromachines.  14 (2023)  11 - p. 2018 , 2023
Link: https://doi.org/10.3390/..
 
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2

Feasibility of Wafer Exchange for European Edge AI Pilot Li..:

, In: Industrial Artificial Intelligence Technologies and Applications,
Wandesleben, Annika Franziska ; Truffier-Boutry, Delphine ; Brackmann, Varvara... - p. 103-112 , 2023
Link: https://doi.org/10.1201/..
 
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3

A Holistic Evaluation of Buried Power Rails and Back-Side P..:

Nibhanupudi, S. S. Teja ; Prasad, Divya ; Das, Shidhartha...
IEEE Transactions on Electron Devices.  69 (2022)  8 - p. 4453-4459 , 2022
Link: https://doi.org/10.1109/..
 
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4

Multitimescale Mitigation for Performance Variability Impro..:

Lin, Ji-Yung ; Weckx, Pieter ; Mishra, Subrat..
IEEE Transactions on Very Large Scale Integration (VLSI) Systems.  30 (2022)  11 - p. 1757-1769 , 2022
Link: https://doi.org/10.1109/..
 
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5

80 nm tall thermally stable cost effective FinFETs for adva..:

Spessot, Alessio ; Ritzenthaler, Romain ; Litta, Eugenio Dentoni...
Japanese Journal of Applied Physics.  60 (2021)  SB - p. SBBB06 , 2021
Link: https://doi.org/10.35848..
 
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6

Correlated Time-0 and Hot-Carrier Stress Induced FinFET Par..:

Makarov, Alexander ; Roussel, Philippe ; Bury, Erik...
Micromachines.  11 (2020)  7 - p. 657 , 2020
Link: https://doi.org/10.3390/..
 
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7

Relevance of fin dimensions and high-pressure anneals on ho..:

, In: 2020 IEEE International Reliability Physics Symposium (IRPS),
Chasin, Adrian ; Franco, Jacopo ; Bury, Erik... - p. 1-6 , 2020
Link: https://doi.org/10.1109/..
 
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8

(Invited) Stress Simulations of Fins, Wires, and Nanosheets:

Eneman, Geert ; Veloso, Anabela ; Favia, Paola...
ECS Transactions.  98 (2020)  5 - p. 253-265 , 2020
Link: https://doi.org/10.1149/..
 
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9

Process, Circuit and System Co-optimization of Wafer Level ..:

, In: Proceedings of the 56th Annual Design Automation Conference 2019,
Huynh-Bao, Trong ; Veloso, Anabela ; Sakhare, Sushil... - p. 1-6 , 2019
Link: https://dl.acm.org/doi/1..
 
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10

Buried Power Rails and Back-side Power Grids: Arm® CPU Powe..:

, In: 2019 IEEE International Electron Devices Meeting (IEDM),
Prasad, Divya ; Teja Nibhanupudi, S. S. ; Das, Shidhartha... - p. 19.1.1-19.1.4 , 2019
Link: https://doi.org/10.1109/..
 
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11

On Correlation between Hot-Carrier Stress Induced Device Pa..:

, In: 2019 IEEE International Integrated Reliability Workshop (IIRW),
Makarov, Alexander ; Roussel, Philippe ; Bury, Erik... - p. 1-4 , 2019
Link: https://doi.org/10.1109/..
 
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12

CMOS integration of high-k/metal gate transistors in diffus..:

Litta, Eugenio Dentoni ; Ritzenthaler, Romain ; Schram, Tom...
Japanese Journal of Applied Physics.  57 (2018)  4S - p. 04FB08 , 2018
Link: https://doi.org/10.7567/..
 
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13

Optimized material solutions for advanced DRAM peripheral t..:

Spessot, Alessio ; Ritzenthaler, Romain ; Schram, Tom..
physica status solidi (a).  213 (2016)  2 - p. 245-254 , 2016
Link: https://doi.org/10.1002/..
 
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14

Optimized material solutions for advanced DRAM peripheral t..:

Spessot, Alessio ; Ritzenthaler, Romain ; Schram, Tom..
physica status solidi (a).  213 (2016)  2 - p. 484-484 , 2016
Link: https://doi.org/10.1002/..
 
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15

Increase in Oxide Trap Density Due to the Implementation of..:

Simoen, Eddy ; Ritzenthaler, Romain ; Cho, Moon Ju...
ECS Transactions.  69 (2015)  10 - p. 281-289 , 2015
Link: https://doi.org/10.1149/..
 
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